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rename_execute_retire: add more tests using unit::alu_branch

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This commit is contained in:
Jacob Lifshay 2026-05-25 21:27:37 -07:00
parent 225ceb0dfa
commit dd2fe36869
Signed by: programmerjake
SSH key fingerprint: SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
3 changed files with 230396 additions and 0 deletions
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91167
crates/cpu/tests/expected/rename_execute_retire_fibonacci_real.vcd generated Normal file
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139152
crates/cpu/tests/expected/rename_execute_retire_slow_loop_real.vcd generated Normal file
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77
crates/cpu/tests/rename_execute_retire.rs
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@ -4270,6 +4270,43 @@ fn test_rename_execute_retire_fibonacci_combinatorial() {
assert!(sim.read_bool(sim.io().all_outputs_written));
}
#[hdl]
#[test]
fn test_rename_execute_retire_fibonacci_real() {
let _n = SourceLocation::normalize_files_for_tests();
let mut config = CpuConfig::new(
vec![
UnitConfig::new(UnitKind::AluBranch),
UnitConfig::new(UnitKind::AluBranch),
UnitConfig::new(UnitKind::AluBranch),
UnitConfig::new(UnitKind::LoadStore),
UnitConfig::new(UnitKind::TransformedMove),
],
NonZeroUsize::new(20).unwrap(),
);
config.fetch_width = NonZeroUsize::new(3).unwrap();
let m = rename_execute_retire_test_harness::<FibonacciInsns>(
PhantomConst::new_sized(config),
AluBranchKind::Real,
);
let mut sim = Simulation::new(m);
let _checked_vcd_output = checked_vcd_output!(
&mut sim,
"tests/expected/rename_execute_retire_fibonacci_real.vcd",
);
sim.write_clock(sim.io().cd.clk, false);
sim.write_reset(sim.io().cd.rst, true);
for cycle in 0..200 {
sim.advance_time(SimDuration::from_nanos(500));
println!("clock tick: {cycle}");
sim.write_clock(sim.io().cd.clk, true);
sim.advance_time(SimDuration::from_nanos(500));
sim.write_clock(sim.io().cd.clk, false);
sim.write_reset(sim.io().cd.rst, false);
}
assert!(sim.read_bool(sim.io().all_outputs_written));
}
struct SlowLoopInsns;
impl SlowLoopInsns {
@ -4389,6 +4426,46 @@ fn test_rename_execute_retire_slow_loop() {
assert!(sim.read_bool(sim.io().started_any_l2_reg_file_ops));
}
#[hdl]
#[test]
fn test_rename_execute_retire_slow_loop_real() {
let _n = SourceLocation::normalize_files_for_tests();
let mut config = CpuConfig::new(
vec![
UnitConfig::new(UnitKind::AluBranch),
UnitConfig::new(UnitKind::AluBranch),
UnitConfig::new(UnitKind::AluBranch),
UnitConfig::new(UnitKind::AluBranch),
UnitConfig::new(UnitKind::LoadStore),
UnitConfig::new(UnitKind::TransformedMove),
],
NonZeroUsize::new(20).unwrap(),
);
config.fetch_width = NonZeroUsize::new(4).unwrap();
let m = rename_execute_retire_test_harness::<SlowLoopInsns>(
PhantomConst::new_sized(config),
AluBranchKind::Real,
);
let mut sim = Simulation::new(m);
let _checked_vcd_output = checked_vcd_output!(
&mut sim,
"tests/expected/rename_execute_retire_slow_loop_real.vcd",
);
sim.write_clock(sim.io().cd.clk, false);
sim.write_reset(sim.io().cd.rst, true);
for cycle in 0..350 {
sim.advance_time(SimDuration::from_nanos(500));
println!("clock tick: {cycle}");
sim.write_clock(sim.io().cd.clk, true);
sim.advance_time(SimDuration::from_nanos(500));
sim.write_clock(sim.io().cd.clk, false);
sim.write_reset(sim.io().cd.rst, false);
}
assert!(sim.read_bool(sim.io().all_outputs_written));
// make sure we're actually testing L2 reg file ops
assert!(sim.read_bool(sim.io().started_any_l2_reg_file_ops));
}
/// equivalent of Unix's `head -n1`
struct HeadN1Insns;