George Rennie 0fcf5c080d Merge pull request #5158 from georgerennie/george/task_inout ... read_verilog/astsimplify: copy inout ports in and out of functions/tasks		2025-06-04 14:23:08 +01:00
..
aiger	aiger: add regression test for sliced output segfault	2025-05-09 16:01:47 +02:00
alumacc
arch	URAM mapping : Add test for 2048 x 144b	2025-05-10 14:53:56 +02:00
asicworld
bind
blif
bram
cxxrtl	Reinstate #4768	2025-04-08 11:58:05 +12:00
errors
fmt
fsm
functional
hana
liberty	libcache: fix test	2025-05-09 12:40:38 +02:00
lut
memfile
memlib
memories
opt	tests: test opt_expr for 32 bit unsigned shifts	2025-05-26 15:28:44 +01:00
opt_share
peepopt	Add muldiv_c peepopt pass	2025-04-30 08:06:59 -07:00
proc
realmath
rpc
sat	share: Cleanup and additional testing	2025-04-15 12:34:46 +02:00
select	design.cc: Fix selections when copying	2025-04-08 16:35:12 +12:00
share
sim	fstdata.cc: Fix last step	2025-05-12 13:18:19 +12:00
simple
simple_abc9	Reinstate #4768	2025-04-08 11:58:05 +12:00
smv
sva
svinterfaces
svtypes	Tests: Add svtypes/typedef_struct_global.ys	2025-05-26 12:16:58 +12:00
techmap	Add check at constmap and merge test	2025-04-14 11:44:52 +01:00
tools
unit	rtlil: Add {from,to}_hdl_index methods to Wire	2025-02-18 17:08:45 +01:00
various	cutpoint: Re-add whole module optimization	2025-05-06 09:57:34 +12:00
verific
verilog	Merge pull request #5158 from georgerennie/george/task_inout	2025-06-04 14:23:08 +01:00
vloghtb
xprop
gen-tests-makefile.sh	Update gen-tests-makefile.sh	2025-03-27 10:33:51 +13:00