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Add check at constmap and merge test

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This commit is contained in:
Kelvin Chung 2025-04-14 11:44:52 +01:00
parent 414dc85573
commit 81f3369f24
2 changed files with 31 additions and 27 deletions
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36
passes/techmap/constmap.cc
View file

@ -33,9 +33,9 @@ void constmap_worker(RTLIL::SigSpec &sig)
{
if (sig.is_fully_const()){
value = module->addWire(NEW_ID, sig.size());
RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype));
cell->setParam(RTLIL::escape_id(cell_paramname), sig.as_const());
cell->setPort(RTLIL::escape_id(cell_portname), value);
RTLIL::Cell *cell = module->addCell(NEW_ID, celltype);
cell->setParam(cell_paramname, sig.as_const());
cell->setPort(cell_portname, value);
sig = value;
}
}
@ -62,15 +62,39 @@ struct ConstmapPass : public Pass {
for (argidx = 1; argidx < args.size(); argidx++)
{
if (args[argidx] == "-cell" && argidx+3 < args.size()){
celltype = args[++argidx];
cell_portname = args[++argidx];
cell_paramname = args[++argidx];
celltype = RTLIL::escape_id(args[++argidx]);
cell_portname = RTLIL::escape_id(args[++argidx]);
cell_paramname = RTLIL::escape_id(args[++argidx]);
continue;
}
break;
}
extra_args(args, argidx, design);
if (design->has(celltype)) {
Module *existing = design->module(celltype);
bool has_port = false;
for (auto &p : existing->ports){
if (p == cell_portname){
has_port = true;
break;
}
}
if (!has_port)
log_cmd_error("Cell type '%s' does not have port '%s'.\n", celltype.c_str(), cell_portname.c_str());
bool has_param = false;
for (auto &p : existing->avail_parameters){
if (p == cell_paramname)
has_param = true;
}
if (!has_param)
log_cmd_error("Cell type '%s' does not have parameter '%s'.\n", celltype.c_str(), cell_paramname.c_str());
}
for (auto mod : design->selected_modules())
{
module = mod;

22
tests/techmap/constmap.ys
View file

@ -9,8 +9,7 @@ endmodule
EOT
constmap -cell const_cell O value
select -assert-count 1 t:const_cell
select -assert-count 1 r:value=16
select -assert-count 1 t:const_cell r:value=16 %i
design -reset
@ -42,22 +41,3 @@ select -assert-count 1 test/out1 %ci* r:value=16 %i
select -assert-count 1 test/out2 %ci* r:value=32 %i
select -assert-count 1 t:const_cell r:value=16 %i
select -assert-count 1 t:const_cell r:value=32 %i
design -reset
read_verilog << EOT
module test();
wire [31:0] in;
wire [31:0] out1;
wire [31:0] out2;
assign out1 = in + 16;
assign out2 = in + 32;
endmodule
EOT
constmap -cell const_cell O value
select -assert-count 1 t:const_cell r:value=16 %i
select -assert-count 1 t:const_cell r:value=32 %i