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dynamic_part_select
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.gitignore
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don't use sed -i because it won't work on macos
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2022-06-03 01:09:57 -07:00 |
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abc9.v
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Another sloppy mistake!
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2019-11-21 16:33:20 -08:00 |
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abc9.ys
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abc9: uniquify blackboxes like whiteboxes (#2695)
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2021-03-29 22:02:06 -07:00 |
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aiger_dff.ys
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async.sh
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async.v
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Fix tests/various/async FFL test
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2019-07-09 22:44:39 +02:00 |
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attrib05_port_conn.v
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attrib05_port_conn.ys
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Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog.
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2019-06-04 10:42:42 +02:00 |
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attrib07_func_call.v
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attrib07_func_call.ys
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autoname.ys
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blackbox_wb.ys
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blackbox: Include whiteboxed modules
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2021-03-17 13:58:04 +00:00 |
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bug1496.ys
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bug1531.ys
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bug1614.ys
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bug1710.ys
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ast: fixes #1710; do not generate RTLIL for unreachable ternary
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2020-02-27 16:55:55 -08:00 |
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bug1745.ys
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bug1781.ys
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fsm_extract: Initialize celltypes with full design.
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2020-03-19 18:51:21 +01:00 |
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bug1876.ys
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bug2014.ys
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test: add test for #2014
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2020-05-02 14:22:37 -07:00 |
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bug3462.ys
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Add test for bug 3462
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2022-08-29 10:10:09 +02:00 |
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bug4082.ys
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cellarray_array_connections.ys
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simplify: regression test for AST_CELLARRAY simplification issue
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2022-12-07 18:41:55 +01:00 |
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celledges_shift.ys
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check.ys
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check: Extend testing
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2024-03-11 10:45:17 +01:00 |
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check_2.ys
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check: Extend testing
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2024-03-11 10:45:17 +01:00 |
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check_3.ys
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check: Rephrase regex for portability
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2024-03-11 10:45:17 +01:00 |
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check_4.ys
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celledges: Add read ports arst paths
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2024-03-11 10:45:17 +01:00 |
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chformal_check.ys
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Additional tests for FV $check compatibility
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2024-02-02 16:07:10 +01:00 |
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chformal_coverenable.ys
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chparam.sh
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clk2fflogic_effects.sh
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clk2fflogic_effects.sv
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clk2fflogic: Fix handling of $check cells
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2024-02-14 11:42:27 +01:00 |
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const_arg_loop.sv
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const_arg_loop.ys
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const_func.sv
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const_func.ys
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tests: Run async2sync before sat and/or sim to handle $check cells
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2024-02-01 16:14:11 +01:00 |
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const_func_block_var.v
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Allow localparams in constant functions
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2020-08-20 20:10:24 -04:00 |
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const_func_block_var.ys
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constant_drive_conflict.ys
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constcomment.ys
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constmsk_test.v
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Added tests/various/constmsk_test.ys
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2014-09-04 15:07:30 +02:00 |
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constmsk_test.ys
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constmsk_testmap.v
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countbits.sv
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countbits.ys
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tests: Run async2sync before sat and/or sim to handle $check cells
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2024-02-01 16:14:11 +01:00 |
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deminout_unused.ys
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design.ys
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design1.ys
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design2.ys
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dynamic_part_select.ys
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Add torture test for (* nowrshmsk *) stride optimization
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2024-01-10 20:28:36 +01:00 |
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elab_sys_tasks.sv
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elab_sys_tasks.ys
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Initial implementation of elaboration system tasks
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2019-05-03 03:10:43 +03:00 |
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equiv_make_make_assert.ys
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equiv_make: Add -make_assert option
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2022-06-24 00:17:02 +01:00 |
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equiv_opt_multiclock.ys
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Add equiv_opt -multiclock
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2019-09-11 13:55:59 +01:00 |
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equiv_opt_undef.ys
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exec.ys
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fib.v
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verilog: improved support for recursive functions
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2020-12-31 18:33:59 -07:00 |
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fib.ys
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fib_tern.v
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fib_tern.ys
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verilog: support recursive functions using ternary expressions
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2021-02-12 14:43:42 -05:00 |
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func_port_implied_dir.sv
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func_port_implied_dir.ys
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sv: complete support for implied task/function port directions
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2020-12-31 16:17:13 -07:00 |
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gen_if_null.v
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gen_if_null.ys
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verilog: significant block scoping improvements
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2021-01-31 09:42:09 -05:00 |
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global_scope.ys
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ast: Fix handling of identifiers in the global scope
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2020-04-16 10:30:07 +01:00 |
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gzip_verilog.v.gz
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gzip_verilog.ys
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Add support for reading gzip'd input files
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2019-07-26 10:23:58 +01:00 |
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help.ys
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tests: Fix invocation of 'help -cells'
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2023-07-10 12:42:09 +02:00 |
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hierarchy.sh
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hierarchy_defer.ys
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hierarchy_generate.ys
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hierarchy_param.ys
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ice40_mince_abc9.ys
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integer_range_bad_syntax.ys
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integer_real_bad_syntax.ys
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json_escape_chars.ys
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fix handling of escaped chars in json backend and frontend
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2022-02-18 17:13:09 +01:00 |
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logger_error.ys
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Added back tests for logger
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2020-03-13 15:00:18 +01:00 |
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logger_fail.sh
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tests: use /usr/bin/env for bash.
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2023-08-12 11:59:39 +10:00 |
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logger_nowarning.ys
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logger_warn.ys
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logger_warning.ys
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logic_param_simple.ys
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mem2reg.ys
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memory_word_as_index.data
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memory_word_as_index.v
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Fix elaboration of whole memory words used as indices
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2020-12-26 21:47:38 -07:00 |
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memory_word_as_index.ys
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muxcover.ys
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muxpack.v
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muxpack.ys
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param_struct.ys
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peepopt.ys
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peepopt: Fix padding for the peepopt_shiftmul_right pattern
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2023-12-06 18:35:44 +01:00 |
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plugin.cc
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plugin.sh
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tests: use yosys-config --datdir instead of hard-coded
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2020-04-22 08:29:45 -07:00 |
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pmgen_reduce.ys
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Add test for pmtest_test "reduce" demo pattern
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2019-08-17 14:05:10 +02:00 |
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pmux2shiftx.v
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Cleanup tests
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2020-02-27 10:17:29 -08:00 |
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pmux2shiftx.ys
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Add #1135 testcase
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2019-06-27 11:02:52 -07:00 |
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port_sign_extend.v
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genrtlil: fix signed port connection codegen failures
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2021-02-05 19:51:30 -05:00 |
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port_sign_extend.ys
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primitives.ys
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printattr.ys
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rand_const.sv
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Allow combination of rand and const modifiers
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2021-01-21 08:42:05 -07:00 |
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rand_const.ys
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reg_wire_error.sv
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reg_wire_error.ys
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reg_wire_error test needs the -sv flag so it is run via a script so it had to be moved out of the tests/simple dir that only runs Verilog files
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2018-06-05 18:00:06 +03:00 |
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rename_scramble_name.ys
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rename: add -scramble-name option to randomly rename selections
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2022-08-08 16:03:28 +01:00 |
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rtlil_z_bits.ys
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run-test.sh
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tests: Centralize test collection and Makefile generation
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2020-09-21 15:07:02 +02:00 |
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scopeinfo.ys
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scratchpad.ys
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script.ys
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sformatf.ys
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shregmap.v
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tests: fix some test warnings
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2020-05-25 10:07:58 -07:00 |
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shregmap.ys
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Remove Xilinx test
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2019-08-22 16:18:07 -07:00 |
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signed.ys
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Revert "Revert PRs #2203 and #2244."
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2020-07-10 09:59:48 +02:00 |
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signext.ys
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sim_const.ys
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specify.v
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verilog: ignore ranges too without -specify
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2020-02-13 17:58:43 -08:00 |
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specify.ys
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src.ys
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verilog: add test
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2020-03-11 06:51:03 -07:00 |
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sta.ys
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struct_access.sv
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struct_access.ys
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tests: Run async2sync before sat and/or sim to handle $check cells
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2024-02-01 16:14:11 +01:00 |
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sub.v
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submod.ys
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Add a quick testcase for unknown modules as inout
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2019-12-09 13:14:46 -08:00 |
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submod_extract.ys
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Added tests/various/submod_extract.ys
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2014-07-26 17:22:18 +02:00 |
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sv_defines.ys
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sv_defines_dup.ys
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sv_defines_mismatch.ys
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Add support for SystemVerilog-style `define to Verilog frontend
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2020-03-27 16:08:26 +00:00 |
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sv_defines_too_few.ys
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sv_implicit_ports.sh
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svalways.sh
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wreduce.ys
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Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"
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2019-08-12 12:06:45 -07:00 |
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write_gzip.ys
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xaiger.ys
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