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Author SHA1 Message Date
clairexen
a10893072b
Merge pull request #2352 from zachjs/const-func-localparam 
Allow localparams in constant functions
 2020-09-01 17:31:48 +02:00
clairexen
c1a6097376
Merge pull request #2366 from zachjs/library-format 
Simple support for %l format specifier
 2020-09-01 17:30:36 +02:00
clairexen
3e1840d036
Merge pull request #2353 from zachjs/top-scope 
Module name scope support
 2020-09-01 17:30:09 +02:00
clairexen
452442ac2f
Merge pull request #2365 from zachjs/const-arg-loop-split-type 
Fix constant args used with function ports split across declarations
 2020-09-01 17:28:35 +02:00
Yosys Bot
244af8b8b7 Bump version 2020-09-01 00:10:06 +00:00
Xiretza
6224fd9055
Add missing gitignores for test artifacts 2020-08-31 19:43:51 +02:00
Miodrag Milanovic
04d5692a85 Reorder to prevent crash 2020-08-31 12:22:26 +02:00
clairexen
d23e4b4dce
Merge pull request #2368 from YosysHQ/verific_portrange 
Fix import of VHDL enums
 2020-08-31 11:58:29 +02:00
Miodrag Milanovic
3af499c60f ast recognize lower case x and z and verific gives upper case 2020-08-30 13:33:03 +02:00
Miodrag Milanovic
2f93579bd1 Do not check for 1 and 0 only 2020-08-30 13:15:06 +02:00
Miodrag Milanovic
b1e3bc059c Fix import of VHDL enums 2020-08-30 12:25:23 +02:00
Yosys Bot
3030c2b46c Bump version 2020-08-30 00:10:07 +00:00
whitequark
c1fff52477
write_smt2: fix SMT-LIB tutorial URL 2020-08-29 20:02:35 +00:00
Zachary Snow
c7ceed3fd3 Simple support for %l format specifier 
Yosys doesn't support libraries, so this provides the same behavior as
%m, as some other tools have opted to do.
 2020-08-29 13:33:31 -04:00
Zachary Snow
ecc5c23b4d Fix constant args used with function ports split across declarations 2020-08-29 13:31:02 -04:00
Yosys Bot
f752023556 Bump version 2020-08-29 00:10:06 +00:00
Dan Ravensloft
028f96e536 intel_alm: better map wide but shallow multiplies 2020-08-28 23:44:16 +02:00
Yosys Bot
c75d8c7439 Bump version 2020-08-28 00:10:07 +00:00
Miodrag Milanović
cc0a4e8f39
Merge pull request #2364 from whitequark/manual-typo 
manual: fix typo
 2020-08-27 18:35:53 +02:00
whitequark
eae88df016 manual: fix typo. 2020-08-27 16:34:48 +00:00
whitequark
a0177569ac
Merge pull request #2357 from whitequark/cxxflags-MP 
Add -MP to CXXFLAGS
 2020-08-27 11:40:57 +00:00
whitequark
2d10d59d93
Merge pull request #2356 from whitequark/flatten-techmap-no-tpl_driven-sigmap 
flatten, techmap: don't canonicalize tpl driven bits via sigmap
 2020-08-27 11:28:31 +00:00
whitequark
702f7c0253
Merge pull request #2358 from whitequark/rename-ilang-to-rtlil 
Replace "ILANG" with "RTLIL" everywhere
 2020-08-27 11:24:06 +00:00
Marcelina Kościelnicka
880df4c897 dfflegalize: Fix decision tree for adffe. 
When an adffe is being legalized, and is not natively supported,
prioritize unmapping to adff over converting to dffsre if dffsre is not
natively supported itself.

Fixes #2361.
 2020-08-27 13:17:42 +02:00
Yosys Bot
925c0f2594 Bump version 2020-08-27 00:10:06 +00:00
Dan Ravensloft
1a07b330f8 intel_alm: Add multiply signedness to cells 
Quartus assumes unsigned multiplication by default, breaking signed
multiplies, so add an input signedness parameter to the MISTRAL_MUL*
cells to propagate to Quartus' <family>_mac cells.
 2020-08-26 22:50:16 +02:00
whitequark
00e7dec7f5 Replace "ILANG" with "RTLIL" everywhere. 
The only difference between "RTLIL" and "ILANG" is that the latter is
the text representation of the former, as opposed to the in-memory
graph representation. This distinction serves no purpose but confuses
people: it is not obvious that the ILANG backend writes RTLIL graphs.

Passes `write_ilang` and `read_ilang` are provided as aliases to
`write_rtlil` and `read_rtlil` for compatibility.
 2020-08-26 17:29:32 +00:00
whitequark
deb19e1574 Add -MP to CXXFLAGS. 
This avoids an issue where deleting or moving headers breaks the next
incremental build until the outdated *.d files are deleted.
 2020-08-26 16:56:10 +00:00
whitequark
9f0892159e flatten, techmap: don't canonicalize tpl driven bits via sigmap. 
For connection `assign a = b;`, `sigmap(a)` returns `b`. This is
exactly the opposite of the desired canonicalization for driven bits.
Consider the following code:

    module foo(inout a, b);
      assign a = b;
    endmodule
    module bar(output c);
      foo f(c, 1'b0);
    endmodule

Before this commit, the inout ports would be swapped after flattening
(and cause a crash while attempting to drive a constant value).

This issue was introduced in 9f772eb9.

Fixes #2183.
 2020-08-26 16:29:42 +00:00
Miodrag Milanović
4f2b78e19a
Merge pull request #2355 from YosysHQ/verific_improvements 
Add formal apps and template generators
 2020-08-26 13:26:34 +02:00
Miodrag Milanovic
fe8226a22d Add formal apps and template generators 2020-08-26 10:39:57 +02:00
whitequark
08a226c9e7
Merge pull request #2351 from pbsds/proc_nomux 
Add -nomux switch to proc
 2020-08-26 08:23:54 +00:00
Yosys Bot
12132b6850 Bump version 2020-08-23 00:10:08 +00:00
clairexen
0f81e27898
Merge pull request #2349 from nmoroze/smt2-bugfix 
Ensure smt2 comments are associated with accessors
 2020-08-22 12:28:39 +02:00
Zachary Snow
6127f22788 Module name scope support 2020-08-20 20:15:08 -04:00
Zachary Snow
74abc3bbfd Allow localparams in constant functions 2020-08-20 20:10:24 -04:00
Yosys Bot
dc20d9e842 Bump version 2020-08-21 00:10:06 +00:00
Marcelina Kościelnicka
082cbcb4c7 synth_intel: Remove incomplete Arria 10 GX support. 
The techmap rules for this target do not work in the first place (note
lack of >2-input LUT mappings), and if proper support is ever added,
it'd be better placed in the synth_intel_alm backend.
 2020-08-21 01:46:06 +02:00
Peder Bergebakken Sundt
656ee70f8e proc: Add -nomux switch 
running proc -nomux will ommit the proc_mux pass
 2020-08-20 22:58:08 +02:00
Noah Moroze
91682d189e Ensure smt2 comments are associated with accessors 2020-08-20 16:00:05 -04:00
Dan Ravensloft
034b9ec716 intel: move Cyclone V support to intel_alm 2020-08-20 18:25:05 +02:00
clairexen
d9dd8bc748
Merge pull request #2347 from YosysHQ/mwk/techmap-shift-fixes 
techmap/shift_shiftx: Remove the "shiftx2mux" special path.
 2020-08-20 16:25:56 +02:00
clairexen
a96df40814
Merge pull request #2344 from YosysHQ/mwk/opt_share-fixes 
opt_share: Refactor, fix some bugs.
 2020-08-20 16:24:53 +02:00
clairexen
1d0d9d5c86
Merge pull request #2337 from YosysHQ/mwk/clean-keep-wire 
opt_clean: Fix module keep rules.
 2020-08-20 16:23:55 +02:00
clairexen
799076af24
Merge pull request #2333 from YosysHQ/mwk/peepopt-shiftmul-signed 
peeopt.shiftmul: Add a signedness check.
 2020-08-20 16:23:07 +02:00
clairexen
6a68b8ed54
Merge pull request #2328 from YosysHQ/mwk/opt_dff-cleanup 
Remove passes redundant with opt_dff
 2020-08-20 16:21:58 +02:00
clairexen
faf8e19511
Merge pull request #2327 from YosysHQ/mwk/techmap-constmap-fix 
techmap.CONSTMAP: Handle outputs before inputs.
 2020-08-20 16:21:09 +02:00
clairexen
16bb3fc8bb
Merge pull request #2326 from YosysHQ/mwk/peeopt-muldiv-sign 
peepopt.muldiv: Add a signedness check.
 2020-08-20 16:19:37 +02:00
clairexen
1cdb533fa5
Merge pull request #2319 from YosysHQ/mwk/techmap-celltype-pattern 
techmap: Add support for [] wildcards in techmap_celltype.
 2020-08-20 16:18:40 +02:00
Marcelina Kościelnicka
50d532f01c techmap/shift_shiftx: Remove the "shiftx2mux" special path. 
Our techmap rules for $shift and $shiftx cells contained a special path
that aimed to decompose the shift LSB-first instead of MSB-first in
select cases that come up in pmux lowering.  This path was needlessly
overcomplicated and contained bugs.

Instead of doing that, just switch over the main path to iterate
LSB-first (except for the specially-handled MSB for signed shifts
and overflow handling).  This also makes the code consistent with
shl/shr/sshl/sshr cells, which are already decomposed LSB-first.

Fixes #2346.
 2020-08-20 12:44:09 +02:00