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@ -92,7 +92,7 @@ in different stages of the synthesis.
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\section{The RTL Intermediate Language}
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All frontends, passes and backends in Yosys operate on a design in RTLIL} representation.
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All frontends, passes and backends in Yosys operate on a design in RTLIL representation.
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The only exception are the high-level frontends that use the AST representation as an intermediate step before generating RTLIL
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data.
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