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Code Activity
12769 commits 122 branches 59 tags 72 MiB
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Author SHA1 Message Date
Krystine Sherwin
f810bd88f5 quicklogic: wildcard asymmetric memory tests 2023-11-30 17:33:13 +01:00
Krystine Sherwin
c54d6b29d3 tests: asymmetric sync rams now correctly asymmetric 
Also both use the same named parameters for better mirroring.
 2023-11-30 17:33:13 +01:00
Krystine Sherwin
cdb20baf1f quicklogic: testing port widths on split rams 2023-11-30 17:33:13 +01:00
Krystine Sherwin
4c03c84fa7 quicklogic: testing 1:4 assymetric memory 2023-11-30 17:33:13 +01:00
Krystine Sherwin
a1073c706e quicklogic: fix double width read 2023-11-30 17:33:13 +01:00
Krystine Sherwin
fbf8607b97 quicklogic: Testing split TDP36K 
Adds `double_sync_ram_sdp` to `common/blockram.v`, providing a test for two disjoint memories.
Refactor python blockram template to take a list of params to support the above.
Also change the smaller single TDP36K tests to also test `port_a_width` value.
 2023-11-30 17:33:13 +01:00
Krystine Sherwin
0cd67ce473 quicklogic: Initial blockram tests 
Use python script to generate tests for both SDP and TDP across multiple sizes of RAM.
Adds sync_ram_sdp_(wwr|wrr) to common blockram.v for double width write and double width read respectively.
 2023-11-30 17:33:13 +01:00
Martin Povišer
fb34167fd4 fixup! quicklogic: Add basic k6n10f tests 2023-11-30 13:43:56 +01:00
Martin Povišer
d11a85fcba fixup! quicklogic: Add basic k6n10f tests 2023-11-30 11:12:55 +01:00
Martin Povišer
193144e68b fixup! quicklogic: Add basic k6n10f tests 2023-11-30 10:45:39 +01:00
Martin Povišer
49cee23128 quicklogic: Add RAM_INIT to specialized BRAM models 2023-11-30 10:41:55 +01:00
Martin Povišer
a47c2aaa97 fixup! quicklogic: Add missing RAM_INIT param on TDP36K sim model 2023-11-30 10:18:48 +01:00
Martin Povišer
e70122b74e fixup! quicklogic: Add basic k6n10f tests 2023-11-29 11:20:16 +01:00
Martin Povišer
6066115d5b quicklogic: Add missing RAM_INIT param on TDP36K sim model 2023-11-29 11:04:34 +01:00
Martin Povišer
04d2f55bec fixup! add qlf_k6n10f architecture + bram inference 2023-11-27 18:28:10 +01:00
Martin Povišer
53bda484f8 quicklogic: Set initial values on inferred TDP36K 2023-11-27 17:43:21 +01:00
Martin Povišer
5bc587c843 quicklogic: Add k6n10f DSP test 2023-11-27 17:43:21 +01:00
Martin Povišer
03b45c883a ql_dsp_io_regs: Fix ID strings, constant detection 2023-11-27 17:27:46 +01:00
Martin Povišer
502559cba4 quicklogic: Fix dffs.ys test 2023-11-27 17:27:46 +01:00
Martin Povišer
9d04201e86 synth_quicklogic: Fix missing FF mapping 2023-11-27 14:22:28 +01:00
Martin Povišer
3e004f7b13 quicklogic: Drop blackbox off adder_carry 2023-11-27 14:21:59 +01:00
Martin Povišer
a3b3333eeb quicklogic: Add basic k6n10f tests 2023-11-27 12:14:48 +01:00
Martin Povišer
90f427c7a8 synth_quiclogic: Fix conditioning of bram passes 2023-11-27 12:05:55 +01:00
Martin Povišer
74296e3d92 quicklogic: Move pp3 tests one level down 2023-11-27 12:05:55 +01:00
Martin Povišer
f84ab98055 ql_dsp_macc: Tune DSP inference code 2023-11-27 12:05:55 +01:00
Martin Povišer
306e688406 ql_dsp_*: Clean up 
Clean up the code up to Yosys standards. Drop detection of
QL_DSP2_MULTADD in io_regs since those cells can't be inferred with
the current flow anyway.
 2023-11-27 12:05:55 +01:00
Martin Povišer
6d7dafe5e5 ql_k6n10f: Remove support for parameter-configured DSP variety 2023-11-27 12:05:55 +01:00
N. Engelhardt
a19ac1bbe1 merge brams_final_map.v into brams_map.v 2023-11-27 12:05:55 +01:00
N. Engelhardt
9ce53ea3e2 add dsp inference 2023-11-27 12:05:53 +01:00
N. Engelhardt
7c0dbc8822 change ql-bram-types pass to use mode parameter; clean up primitive libraries 2023-11-27 12:05:52 +01:00
N. Engelhardt
688455ef69 add qlf_k6n10f architecture + bram inference 
(Copied from QuickLogic Yosys plugin repo)
 2023-11-27 12:05:45 +01:00
N. Engelhardt
e230a871be synth_quicklogic: rearrange files to prepare for adding more architectures 2023-11-27 08:37:33 +01:00
github-actions[bot]
031ad38b5c Bump version 2023-11-24 00:15:38 +00:00
Miodrag Milanović
5e603c2241
Merge pull request #4042 from YosysHQ/verific_cell 
Verific: Add attributes to module instantiation
 2023-11-23 11:38:01 +01:00
Miodrag Milanovic
8f207eed1b Add attributes to module instantiation 2023-11-23 11:01:49 +01:00
github-actions[bot]
c95298225d Bump version 2023-11-21 00:16:08 +00:00
Martin Povišer
34f851f132
Merge pull request #4040 from povik/fmt-time 
fmt: Handle free-standing time arguments
 2023-11-20 18:11:24 +01:00
Martin Povišer
282ce24eec fmt: Handle free-standing time arguments 2023-11-20 17:25:42 +01:00
Jannis Harder
b23a607421
Merge pull request #4035 from jix/smtbmc-incremental 
smtbmc: Add --incremental mode
 2023-11-20 17:00:29 +01:00
Miodrag Milanović
191ac91951
Merge pull request #4031 from nakengelhardt/nak/fix_vhdl_blackbox_nullptr 
verific: don't try to import attributes from nullptr
 2023-11-20 15:37:01 +01:00
github-actions[bot]
ab6c1d368b Bump version 2023-11-18 00:15:31 +00:00
N. Engelhardt
fa5fb811df
Merge pull request #4037 from YosysHQ/lofty/ice40-abc9-oopsie 
ice40: fix -noabc9
 2023-11-17 14:36:16 +01:00
Lofty
5c96746309 ice40: fix -noabc9 2023-11-17 12:49:17 +00:00
Jannis Harder
e319606ec9 smtbmc: Add --incremental mode 2023-11-16 13:22:17 +01:00
N. Engelhardt
032fab1f54
Merge pull request #4032 from YosysHQ/lofty/gowin-abc9-oopsie 
gowin: fix typo
 2023-11-15 11:07:49 +01:00
github-actions[bot]
7eea047793 Bump version 2023-11-15 00:15:49 +00:00
Lofty
309558767d gowin: fix typo 2023-11-14 22:37:29 +00:00
N. Engelhardt
5fb1264db5 verific: don't try to import attributes from nullptr 2023-11-14 15:05:24 +01:00
Catherine
c11744b4ef
Fix WASI compilation flags for abc. 2023-11-14 03:33:35 +00:00
Catherine
726c501e7e Update WASI compilation flags to include required libraries 2023-11-14 02:05:39 +00:00