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Code Activity
12260 commits 122 branches 59 tags 72 MiB
Commit graph

86 commits

Author SHA1 Message Date
Pepijn de Vos
0e5dbc4abc fix wide luts 2019-11-06 19:48:18 +01:00
Pepijn de Vos
0f6269b04c add IOBUF 2019-10-28 15:33:05 +01:00
Pepijn de Vos
903f997391 add tristate buffer and test 2019-10-28 15:18:01 +01:00
Pepijn de Vos
2f5e9e9885 More formatting 2019-10-28 13:10:12 +01:00
Pepijn de Vos
c1921b4561 really really fix formatting maybe 2019-10-28 13:01:20 +01:00
Pepijn de Vos
293b2c2de5 undo formatting fuckup 2019-10-28 12:57:12 +01:00
Pepijn de Vos
f88335a8a5 add wide luts 2019-10-28 12:49:08 +01:00
Pepijn de Vos
5fad53b504 add 32-bit BRAM and byte-enables 2019-10-28 10:33:27 +01:00
Pepijn de Vos
8226f2db0b ALU sim tweaks 2019-10-24 13:39:43 +02:00
Pepijn de Vos
03457ee13e add a few more missing dff 2019-10-21 16:08:13 +02:00
Pepijn de Vos
8a2699c40c add negedge DFF 2019-10-21 12:31:11 +02:00
Pepijn de Vos
af7bdd598e use ADDSUB ALU mode to remove inverters 2019-10-21 12:00:27 +02:00
Pepijn de Vos
72323e11a4 remove duplicate DFFR 2019-10-16 11:24:56 +02:00
Pepijn de Vos
2fb20f184a Revert "add MUX support" 
It turns out that they make everything worse and they don't PnR.

This reverts commit 3eff2271d0.
 2019-09-06 11:28:17 +02:00
Pepijn de Vos
96efa63f16 fix BRAM width and init 2019-09-06 10:55:04 +02:00
Pepijn de Vos
1b9f7f49b5 add more DFF to sim lib 2019-09-06 09:01:07 +02:00
Pepijn de Vos
5168b6ffa4 WIP aditional DFF primitives 2019-09-05 19:12:47 +02:00
Pepijn de Vos
47374a495d support bram initialisation 2019-09-05 17:25:51 +02:00
Pepijn de Vos
7a43be5e43 use singleton ground and vcc nets, apparently this makes pnr happier 2019-09-05 16:38:47 +02:00
Pepijn de Vos
3eff2271d0 add MUX support 2019-09-05 13:36:41 +02:00
Pepijn de Vos
ae93c034ad set undriven pads to zero 2019-09-04 16:29:40 +02:00
Pepijn de Vos
a6d81a8d14 Merge remote-tracking branch 'diego/gowin' 2019-09-04 11:20:05 +02:00
Pepijn de Vos
ec56438cf2 gowin: add splitnets to appease the PnR 2019-09-04 10:33:47 +02:00
Diego H
5aa8d7ceeb Updating gowin 2019-09-02 17:43:27 -05:00
Miodrag Milanovic
28b7053a01 Fix formatting for msys2 mingw build using GetSize 2019-08-01 17:27:34 +02:00
Clifford Wolf
913659d644 Merge branch 'master' of https://github.com/dh73/yosys_gowin into dh73-master 2019-04-22 09:09:27 +02:00
Diego
f9272fc56d GoWin enablement: DRAM, initial BRAM, DRAM init, DRAM sim and synth_gowin flow 2019-04-12 23:40:02 -05:00
Miodrag Milanovic
df92e9bdc2 Make nobram false by default for gowin 2019-04-02 19:21:01 +02:00
Larry Doolittle
e2fc18f27b Reduce amount of trailing whitespace in code base 2019-02-28 14:58:11 -08:00
Miodrag Milanovic
3b17c9018a Unify usage of noflatten among architectures 2019-01-04 11:37:25 +01:00
whitequark
efa278e232 Fix typographical and grammatical errors and inconsistencies. 
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.

    DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
    DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
    codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint

More hits were found by looking through comments and strings manually.
 2019-01-02 13:12:17 +00:00
Diego H
819ca73096 Changes in GoWin synth commands and ALU primitive support 2018-12-03 20:08:35 -06:00
Henner Zeller
3aa4484a3c Consistent use of 'override' for virtual methods in derived classes. 
o Not all derived methods were marked 'override', but it is a great
  feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
  provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
  use the plain keyword going forward now that C++11 is established)
 2018-07-20 23:51:06 -07:00
Clifford Wolf
e9d73d2ee0 Indenting fixes in gowin sim cell lib 2016-11-08 18:54:00 +01:00
Clifford Wolf
3db2ac4e00 Added hex constant support to write_verilog 2016-11-03 12:13:23 +01:00
Clifford Wolf
cae5131bac Added initial version of "synth_gowin" 2016-11-01 11:31:13 +01:00