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Updating gowin
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@ -45,7 +45,7 @@ module _80_gw1n_alu(A, B, CI, BI, X, Y, CO);
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genvar i;
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generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
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ALU #(.ALU_MODE(32'b0))
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ALU #(.ALU_MODE(0))
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alu(.I0(AA[i]),
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.I1(BB[i]),
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.I3(1'b0),
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@ -226,7 +226,7 @@ struct SynthGowinPass : public ScriptPass
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if (check_label("vout"))
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{
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if (!vout_file.empty() || help_mode)
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run(stringf("write_verilog -nodec -attr2comment -defparam -renameprefix gen %s",
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run(stringf("write_verilog -nohex -decimal -attr2comment -defparam -renameprefix gen %s",
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help_mode ? "<file-name>" : vout_file.c_str()));
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}
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}
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