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Code Activity
14856 commits 122 branches 59 tags 72 MiB
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312 commits

Author SHA1 Message Date
Martin Povišer
a5c8d246f7 quicklogic: Add k6n10f DSP test 2023-12-04 15:52:03 +01:00
Martin Povišer
db9e5b4f14 quicklogic: Fix dffs.ys test 2023-12-04 15:52:03 +01:00
Martin Povišer
554d8caef7 quicklogic: Add basic k6n10f tests 2023-12-04 15:52:03 +01:00
Martin Povišer
6672b6c1b3 quicklogic: Move pp3 tests one level down 2023-12-04 15:52:02 +01:00
N. Engelhardt
98769010af synth_quicklogic: rearrange files to prepare for adding more architectures 2023-12-04 15:52:02 +01:00
Lofty
7ae4041e20 ice40, ecp5, gowin: enable ABC9 by default 2023-11-13 15:28:13 +00:00
Lofty
b8b47f7c6c
Revert "ice40, ecp5: enable ABC9 by default" 2023-11-03 14:52:52 +00:00
Lofty
32082477b5 ice40, ecp5: enable ABC9 by default 2023-11-03 08:52:54 +00:00
Martin Povišer
62d6338688 quicklogic: Fix pp3 dffs test 
Fix name confusion which was making the test look into the vendor's cell
blackbox rather than into the synthesis results.
 2023-10-12 12:45:40 +02:00
Miodrag Milanovic
a42c630264 put back previous test state, due to default change 2023-08-29 10:21:58 +02:00
Miodrag Milanovic
3b9ebfa672 Addressed code review comments 2023-08-25 11:10:20 +02:00
Miodrag Milanovic
ea50d96135 fixed tests 2023-08-23 10:54:29 +02:00
Charlotte
d130f7fca2 tests: use /usr/bin/env for bash. 2023-08-12 11:59:39 +10:00
Miodrag Milanovic
e6f7cf3b29 Update tests 2023-06-09 14:41:45 +02:00
Eddie Hung
862631d657 Add ABC9 DSP cascade test 2023-05-25 18:42:08 +01:00
Lofty
00b0e850db intel_alm: re-enable carry chains for ABC9 2023-05-25 18:28:10 +01:00
Ralf Fuest
30f1d10948 gowin: Fix X output of $alu techmap 2023-05-01 17:56:41 +02:00
Benjamin Barzen
8611429237
ABC9: Cell Port Bug Patch (#3670) 
* ABC9: RAMB36E1 Bug Patch

* Add simplified testcase

* Also fix xaiger writer for under-width output ports

* Remove old testcase

* Missing top-level input port

* Fix tabs

---------

Co-authored-by: Eddie Hung <eddie@fpgeh.com>
 2023-04-22 16:24:36 -07:00
Miodrag Milanovic
0f5e7c244d add additional dff and lutram tests 2023-04-06 09:10:14 +02:00
Miodrag Milanovic
54d313efc3 add test for CCU2D 2023-04-06 09:10:14 +02:00
Miodrag Milanovic
61da330a38 Update tests 2023-03-20 09:58:41 +01:00
gatecat
2ab3747cc9 fabulous: Add support for mapping carry chains 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-02-27 09:50:34 +01:00
KrystalDelusion
f80920bd9f Genericising bug1836.ys 2023-02-21 05:23:16 +13:00
KrystalDelusion
445a801a85 bug3205.ys removed 
Made redundant by TDP test(s) in memories.ys
 2023-02-21 05:23:16 +13:00
KrystalDelusion
51c2d476c2 Removing extra default_nettype lines 2023-02-21 05:23:16 +13:00
KrystalDelusion
8f6a06951c Fix for sync_ram_sdp not being final module 
Explicitly declare -top in synth_intel_alm.
 2023-02-21 05:23:16 +13:00
KrystalDelusion
af1b9c9e07 Tests for ram_style = "huge" 
iCE40 SPRAM and Xilinx URAM
 2023-02-21 05:23:15 +13:00
KrystalDelusion
de2f140c09 Testing TDP synth mapping 
New common sync_ram_tdp.
Used in ecp5 and gatemate mem*.ys.
 2023-02-21 05:23:15 +13:00
KrystalDelusion
48f4e09202 Asymmetric port ram tests with Xilinx 
Uses verilog code from User Guide 901 (2021.1)
 2023-02-21 05:23:14 +13:00
KrystalDelusion
ac5fa9a838 Addings tests for #1836 and #3205 2023-02-21 05:23:14 +13:00
gatecat
b6467f0801 fabulous: Allow adding extra custom prims and map rules 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-11-17 13:34:58 +01:00
gatecat
f111bbdf40 fabulous: improvements to the pass 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-11-17 13:34:58 +01:00
Jannis Harder
0113f44faa Reenable existing equiv_opt tests 2022-10-07 16:04:51 +02:00
Jannis Harder
81906aa627 Fix tests for check in equiv_opt 2022-10-07 16:04:51 +02:00
Miodrag Milanovic
f4a1906721 support file locations containing spaces 2022-08-08 20:30:50 +02:00
gatecat
48efc9b75c gatemate: Add test for LUT tree mapping 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-06-27 10:09:48 +01:00
Marcelina Kościelnicka
9d11575856 efinix: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka
d7dc2313b9 ice40: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka
3b2f95953c xilinx: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka
0a8eaca322 nexus: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka
a04b025abf ecp5: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
Lofty
9f7a55c99f intel_alm: M10K write-enable is negative-true 2022-03-09 20:18:06 +00:00
Marcelina Kościelnicka
f61f2a4078 gowin: Fix LUT RAM inference, add more models. 2022-02-09 09:04:34 +01:00
Icenowy Zheng
c2b7ad3b28 anlogic: support BRAM mapping 
Anlogic FPGAs all have two kinds of BRAMs, one is 9bit*1K when being
true dual port (or 18bit*512 when simple dual port), the other is
16bit*2K.

Supports mapping of these two kinds of BRAMs. 9Kbit BRAM in SDP mode and
32Kbit BRAM with 8bit width are not support yet.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
 2021-12-17 20:28:22 +08:00
Claire Xenia Wolf
d6e4d3f1ba Fix the tests we just broke 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-12-10 00:22:37 +01:00
Miodrag Milanovic
d65942b9ac Add gitignore for gatemate 2021-12-03 09:56:37 +01:00
Patrick Urban
81964d6d6f synth_gatemate: Update pass 
* remove `write_edif` and `write_blif` options
* remove redundant `abc` call before muxcover
* update style
 2021-11-13 21:53:25 +01:00
Patrick Urban
97d03c2b3b synth_gatemate: Apply new test practice with assert-max 2021-11-13 21:53:25 +01:00
Patrick Urban
76bf96d310 synth_gatemate: Fix fsm test 2021-11-13 21:53:25 +01:00
Patrick Urban
acb993b27b Allow initial blocks to be disabled during tests 
Wrap initial blocks with a NO_INIT so that tests for archs without register initialization feature don't fail.
 2021-11-13 21:53:25 +01:00