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Code Activity
yosys/tests/arch
History
KrystalDelusion af1b9c9e07 Tests for ram_style = "huge" 
iCE40 SPRAM and Xilinx URAM
2023-02-21 05:23:15 +13:00
..
anlogic anlogic: support BRAM mapping 2021-12-17 20:28:22 +08:00
common Testing TDP synth mapping 2023-02-21 05:23:15 +13:00
ecp5 Testing TDP synth mapping 2023-02-21 05:23:15 +13:00
efinix efinix: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
fabulous fabulous: Allow adding extra custom prims and map rules 2022-11-17 13:34:58 +01:00
gatemate Testing TDP synth mapping 2023-02-21 05:23:15 +13:00
gowin gowin: Fix LUT RAM inference, add more models. 2022-02-09 09:04:34 +01:00
ice40 Tests for ram_style = "huge" 2023-02-21 05:23:15 +13:00
intel_alm Reenable existing equiv_opt tests 2022-10-07 16:04:51 +02:00
machxo2 iopadmap: Add native support for negative-polarity output enable. 2021-11-09 15:40:16 +01:00
nexus nexus: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
quicklogic quicklogic: ABC9 synthesis 2021-04-17 20:54:58 +02:00
xilinx Tests for ram_style = "huge" 2023-02-21 05:23:15 +13:00
run-test.sh Add default assignments to SB_LUT4 2021-04-20 12:46:21 +02:00