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Author SHA1 Message Date
Muthiah Annamalai (முத்து அண்ணாமலை)
f3d2a8dfcc
Merge branch 'YosysHQ:master' into rtlworks/script-stack/issue/3594 2023-05-29 11:27:50 -07:00
Lofty
fb7af093a8 intel_alm: re-enable 8x40-bit M10K support 2023-05-29 06:42:03 +01:00
github-actions[bot]
8596c5ce49 Bump version 2023-05-26 00:15:52 +00:00
Lofty
cac1bc6fbe intel_alm: enable M10K initialisation 2023-05-25 18:56:34 +01:00
Eddie Hung
ec8d7b1c68 abc9_ops -prep_hier to unmap entire module 2023-05-25 18:42:08 +01:00
Eddie Hung
862631d657 Add ABC9 DSP cascade test 2023-05-25 18:42:08 +01:00
Lofty
00b0e850db intel_alm: re-enable carry chains for ABC9 2023-05-25 18:28:10 +01:00
gatecat
52c8c28d2c Add recover_names pass to recover names post-mapping 2023-05-25 10:55:07 +02:00
github-actions[bot]
57c9eb70fe Bump version 2023-05-24 00:15:32 +00:00
Miodrag Milanović
5e36effe3c
Merge pull request #3777 from YosysHQ/micko/vhdl_verific 
Fix importing parametrized VHDL entity
 2023-05-23 11:44:49 +02:00
Miodrag Milanovic
ecd289c100 Fix importing parametrized VHDL entity 2023-05-23 08:25:08 +02:00
Jannis Harder
4f3d1be96a
Merge pull request #3767 from YosysHQ/krys/yw_fix 
Assign wires an smtoffset
 2023-05-22 16:10:55 +02:00
Jannis Harder
5fb1223861
Merge pull request #3733 from AdamHillier/aiger-inputs 
Add outputs before inputs to the sigmap in the AIGER backend.
 2023-05-22 16:09:15 +02:00
N. Engelhardt
890849447f
Merge pull request #3716 from antmicro/kr/brackets 2023-05-22 16:06:38 +02:00
github-actions[bot]
cdeef5481c Bump version 2023-05-22 00:16:53 +00:00
CORRADI Quentin
e7156c644d Standard compliance for tests/verilog/block_labels.ys 
genvar declaration cannot take an initial value when declared as a module_or_generate_item_declaration.
Correct this test so that it doesn't fail unexpectedly if Yosys aligns with the standard.
 2023-05-21 16:38:14 -04:00
Muthiah Annamalai (முத்து அண்ணாமலை)
7ae0b8c832
Merge branch 'YosysHQ:master' into rtlworks/script-stack/issue/3594 2023-05-20 22:49:45 -07:00
Jannis Harder
ad2b04d63a sim: Fix cosimulation with nested modules having unconnected inputs 
When assigning values to input ports of nested modules in cosimulation,
sim needs to find the actual driver of the signal to perform the
assignment. The existing code didn't handle unconnected inputs in that
scenario.
 2023-05-18 16:50:11 +02:00
Jannis Harder
e6f3914800 smt2: Use smt bv offset for $any*'s smtoffset 
While not setting the smtoffset here was clearly a bug, I think using
`chunk.offset` only worked incidentally. The `smtoffset` is an offset
into the `smtname, smtid` pair (here `"", idcounter`) which corresponds
to the smt bitvector `stringf("%s#%d", get_id(module), idcounter)` which
contains all the chunks this loop is iterating over.

Thus using an incrementing `smtoffset` (like the `$ff`/`$dff` case above
already does) should be the correct fix.
 2023-05-18 11:58:09 +02:00
github-actions[bot]
147cceb516 Bump version 2023-05-18 00:15:34 +00:00
Krystine Sherwin
52ad7a47f3
Assign wires an smtoffset 
Wires weren't being assigned an smtoffset value so when generating a yosys witness trace it would also use an offset of 0.
Not sure if this has any other effects, but it fixes the bug I was having.
@jix could you take a look at this?
 2023-05-18 10:37:55 +12:00
Muthu Annamalai
026cbcdd28 keep script-stack error logging 2023-05-17 16:49:50 +00:00
Muthiah Annamalai (முத்து அண்ணாமலை)
8d894d1100
Merge branch 'YosysHQ:master' into rtlworks/issue/3594 2023-05-17 09:24:26 -07:00
Miodrag Milanovic
c2285b3460 fix file rights 2023-05-17 13:39:57 +02:00
Miodrag Milanović
07e76fcaca
Merge pull request #3751 from RTLWorks/main/issue2525 
[YOSYS-2525] fix read_liberty newline handling #2525
 2023-05-17 13:33:34 +02:00
Muthiah Annamalai (முத்து அண்ணாமலை)
693c609eec
Merge branch 'YosysHQ:master' into main/issue2525 2023-05-16 21:21:32 -07:00
Muthu Annamalai
665e0f6131 remove new line per maintainer request 2023-05-17 04:20:13 +00:00
Miodrag Milanović
acfdc5cc42
Merge pull request #3755 from RTLWorks/muthu/issue3498 
[YOSYS] Issue #3498 - Fix Synopsys style unquoted Liberty style
 2023-05-15 16:34:35 +02:00
Muthu Annamalai
721bd82d6f yosys> read_verilog /tmp/powerlog/cloud/Powerlog_43077FB1-54B7-4948-9CE7-C8A2DBD19124.tar.gz 
Found gzip magic in file /tmp/powerlog/cloud/Powerlog_43077FB1-54B7-4948-9CE7-C8A2DBD19124.tar.gz, decompressing using zlib.

1. Executing Verilog-2005 frontend: /tmp/powerlog/cloud/Powerlog_43077FB1-54B7-4948-9CE7-C8A2DBD19124.tar.gz
Parsing Verilog input from `/tmp/powerlog/cloud/Powerlog_43077FB1-54B7-4948-9CE7-C8A2DBD19124.tar.gz' to AST representation.
/tmp/powerlog/cloud/Powerlog_43077FB1-54B7-4948-9CE7-C8A2DBD19124.tar.gz:1: ERROR: syntax error, unexpected TOK_ID
Obtained 13 stack frames.
1 | 0   yosys                               0x00000001001644ac _Z17yosys_print_tracev + 88
2 | 1   yosys                               0x0000000100164568 _Z12yosys_atexitv + 16
3 | 2   yosys                               0x0000000100205124 _ZN5YosysL22logv_error_with_prefixEPKcS1_Pc + 840
4 | 3   yosys                               0x00000001002052f4 _ZN5Yosys14log_file_errorERKNSt3__112basic_stringIcNS0_11char_traitsIcEENS0_9allocatorIcEEEEiPKcz + 96
5 | 4   yosys                               0x00000001003bc694 _ZNSt3__110__list_impINS_6vectorINS_12basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEEENS5_IS7_EEEENS5_IS9_EEE5clearEv + 0
6 | 5   yosys                               0x000000010039772c _Z24frontend_verilog_yyparsev + 2164
7 | 6   yosys                               0x00000001003be520 _ZN5Yosys15VerilogFrontend7executeERPNSt3__113basic_istreamIcNS1_11char_traitsIcEEEENS1_12basic_stringIcS4_NS1_9allocatorIcEEEENS1_6vectorISB_NS9_ISB_EEEEPNS_5RTLIL6DesignE + 5556
8 | 7   yosys                               0x0000000100171c60 _ZN5Yosys8Frontend7executeENSt3__16vectorINS1_12basic_stringIcNS1_11char_traitsIcEENS1_9allocatorIcEEEENS6_IS8_EEEEPNS_5RTLIL6DesignE + 172
9 | 8   yosys                               0x00000001001709a4 _ZN5Yosys4Pass4callEPNS_5RTLIL6DesignENSt3__16vectorINS4_12basic_stringIcNS4_11char_traitsIcEENS4_9allocatorIcEEEENS9_ISB_EEEE + 532
10 | 9   yosys                               0x0000000100170464 _ZN5Yosys4Pass4callEPNS_5RTLIL6DesignENSt3__112basic_stringIcNS4_11char_traitsIcEENS4_9allocatorIcEEEE + 1080
11 | 10  yosys                               0x000000010021479c _ZN5Yosys5shellEPNS_5RTLIL6DesignE + 320
12 | 11  yosys                               0x0000000100165374 main + 3444
13 | 12  dyld                                0x00000001016710f4 start + 520
 2023-05-13 00:49:05 -07:00
Muthu Annamalai
e5c89b641c Merge branch 'muthu/issue/3594' of ssh://143.244.178.245:/home/muthu/devel/yosys into rtlworks/issue/3594 2023-05-10 10:55:49 -07:00
Muthu Annamalai
7c4609aa7a [Backtrace] enable compile flag to trigger on at-exit; 6 frame minimum shows clean atexit when there is not much of a stack 
Obtained 6 stack frames.
1 | ./yosys(_Z17yosys_print_tracev+0x2e) [0x55c7a207830a]
2 | ./yosys(_Z12yosys_atexitv+0x9) [0x55c7a2078386]
3 | ./yosys(main+0x1c33) [0x55c7a207a020]
4 | /lib/x86_64-linux-gnu/libc.so.6(+0x23510) [0x7fae3a623510]
5 | /lib/x86_64-linux-gnu/libc.so.6(__libc_start_main+0x89) [0x7fae3a6235c9]
6 | ./yosys(_start+0x25) [0x55c7a2078215]
 2023-05-10 17:54:36 +00:00
Muthu Annamalai
a52aeb0396 Merge remote-tracking branch 'origin/master' into muthu/issue/3594 2023-05-10 16:56:37 +00:00
Kamil Rakoczy
6b3e6d96a3 Fix missing brackets around else 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2023-05-10 08:09:11 +02:00
github-actions[bot]
d82bae32be Bump version 2023-05-10 00:15:03 +00:00
Muthiah Annamalai (முத்து அண்ணாமலை)
c855502bd5
Update passes/techmap/libparse.cc 
Allow Liberty canonical identifier including double quotes in if-body and pass-through for Synopsys-style unquoted identifiers issue#3498

Co-authored-by: Aki <201479+lethalbit@users.noreply.github.com>
 2023-05-09 06:40:21 -07:00
Miodrag Milanović
7aab324e85
Merge pull request #3737 from yrabbit/all-primitives-script 
gowin: Add all the primitives.
 2023-05-09 11:13:51 +02:00
Miodrag Milanović
5c7cc6ff06
Merge pull request #3745 from rfuest/gowin_alu 
gowin: Fix X output of $alu techmap
 2023-05-09 11:12:50 +02:00
Miodrag Milanović
226a224640
Merge pull request #3749 from lethalbit/aki/plugin-stuff 
Updated the `plugin` command to better handle paths
 2023-05-09 08:46:02 +02:00
Miodrag Milanovic
f790e00478 Next dev cycle 2023-05-09 08:00:06 +02:00
Miodrag Milanovic
9c5a60eb20 Release version 0.29 2023-05-09 07:57:55 +02:00
Muthu Annamalai
8b2994a05a [YOSYS][Issue 3594] Print backtrace on abort/assert #3594 
ERROR: No such command: prox (type help for a command overview)
Error while executing script:
	Running script on file demo.ys
---------------------------------
   1 read_verilog ./tests/lut/map_not.v
   2 opt
   3 proc_clean
-->4 prox
---------------------------------
 2023-05-08 22:37:49 -07:00
Muthu Annamalai
dd5a56128a [YOSYS][Issue 3594] Print backtrace on abort/assert #3594 
ERROR: No such command: prox (type help for a command overview)
Error while executing script:
	Running script on file demo.ys
---------------------------------
   1 read_verilog ./tests/lut/map_not.v
   2 opt
   3 proc_clean
-->4 prox
---------------------------------
 2023-05-09 05:30:20 +00:00
github-actions[bot]
0469405abf Bump version 2023-05-09 00:15:34 +00:00
N. Engelhardt
266036c6f9
Merge pull request #3756 from YosysHQ/krys/sim_writeback 2023-05-08 16:21:24 +02:00
N. Engelhardt
0aeb6105eb
Merge pull request #3736 from jix/conc_assertion_in_unclocked_proc_ctx 2023-05-08 16:15:13 +02:00
N. Engelhardt
ec56e625f4
Merge pull request #3742 from jix/fix_rename_witness_cell_renames 2023-05-08 16:13:28 +02:00
Krystine Sherwin
5a4e72f57a
Fix sim writeback check for yw_cosim 
Writeback of simulation state into initial state was only working for `run()` and `run_cosim_fst()`.
This change moves the writeback into the `write_output_files()` function so that all simulation modes work with the writeback option.
 2023-05-08 13:13:09 +12:00
Muthu Annamalai
17cfc969dd [YOSYS] Issue #3498 - Fix Synopsys style unquoted Liberty style function body parsing with unittest 2023-05-06 23:37:47 -07:00
YRabbit
8341fd450e Merge branch 'master' into all-primitives-script 2023-05-07 05:58:35 +10:00
Miodrag Milanović
4251d37f4f
Merge pull request #3610 from YosysHQ/synthprop 
Synthesizable properties
 2023-05-05 11:03:09 +02:00