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Code Activity
15869 commits 122 branches 59 tags 73 MiB
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2006 commits

Author SHA1 Message Date
whitequark
d22888ce74 read_ilang: improve error message for overly long wires. 
Fixes #1838.
 2020-04-06 10:33:02 +00:00
whitequark
ca70a1049f read_ilang: detect overflow of integer literals. 2020-04-06 10:32:02 +00:00
Eddie Hung
cf716e1fff
Merge pull request #1853 from YosysHQ/eddie/fix_dynslice 
ast: cap dynamic range select to size of signal, suppresses warnings
 2020-04-02 12:27:10 -07:00
Eddie Hung
5f662b1c43
Merge pull request #1767 from YosysHQ/eddie/idstrings 
IdString: use more ID::*, make them easier to use, speed up IdString::in()
 2020-04-02 11:47:25 -07:00
Eddie Hung
956ecd48f7 kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
Claire Wolf
c69f4b246a
Merge pull request #1846 from dh73/ast_fe 
Adding error message for when size (width) of number literal is zero
 2020-04-02 18:15:15 +02:00
Eddie Hung
fdafb74eb7 kernel: use more ID::* 2020-04-02 07:14:08 -07:00
Eddie Hung
37f42fe102
Merge pull request #1845 from YosysHQ/eddie/kernel_speedup 
kernel: speedup by using more pass-by-const-ref
 2020-04-02 07:13:33 -07:00
David Shah
f3405e7c79
Merge pull request #1844 from YosysHQ/dave/gen-source-loc 
verilog: Add location info for generate constructs
 2020-04-01 20:55:24 +01:00
David Shah
c3997c77a5 verilog: Add location info for generate constructs 
Signed-off-by: David Shah <dave@ds0.me>
 2020-04-01 18:47:20 +01:00
Eddie Hung
c22fb76664 ast: cap dynamic range select to size of signal, suppresses warnings 2020-04-01 09:59:23 -07:00
Claire Wolf
926a010b49
Merge pull request #1848 from YosysHQ/eddie/fix_dynslice 
ast: simplify to fully populate dynamic slicing case transformation
 2020-04-01 08:38:14 +02:00
Eddie Hung
5132f4099b ast: simplify to fully populate dynamic slicing case transformation 2020-03-31 11:52:14 -07:00
Diego H
c859bcf71b Replacing log_error for log_file_error due consistency 2020-03-31 12:01:29 -06:00
Diego H
92809bb1d3 Adding error message for when size (width) of number literal is zero 2020-03-30 17:18:13 -06:00
Eddie Hung
05f74d4f31
Merge pull request #1783 from boqwxp/astcc_cleanup 
Clean up pseudo-private member usage in `frontends/ast/ast.cc`.
 2020-03-30 13:06:10 -07:00
Alberto Gonzalez
b538c6fbf2
Add explanatory comment about inefficient wire removal and remove superfluous call to fixup_ports(). 
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
 2020-03-30 18:14:32 +00:00
N. Engelhardt
d5e2061687
Merge pull request #1811 from PeterCrozier/typedef_scope 
Support module/package/interface/block scope for typedef names.
 2020-03-30 13:55:39 +02:00
N. Engelhardt
2c847e7efe
Merge pull request #1778 from rswarbrick/sv-defines 
Add support for SystemVerilog-style `define to Verilog frontend
 2020-03-30 13:51:12 +02:00
Claire Wolf
1bf2bdf05b
Merge pull request #1607 from whitequark/simplify-simplify-meminit 
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT
 2020-03-27 17:28:26 +01:00
Peter Crozier
f8c065ed1c Inline productions to follow house style. 2020-03-27 16:21:45 +00:00
Rupert Swarbrick
044ca9dde4 Add support for SystemVerilog-style `define to Verilog frontend 
This patch should support things like

  `define foo(a, b = 3, c)   a+b+c

  `foo(1, ,2)

which will evaluate to 1+3+2. It also spots mistakes like

  `foo(1)

(the 3rd argument doesn't have a default value, so a call site is
required to set it).

Most of the patch is a simple parser for the format in preproc.cc, but
I've also taken the opportunity to wrap up the "name -> definition"
map in a type, rather than use multiple std::map's.

Since this type needs to be visible to code that touches defines, I've
pulled it (and the frontend_verilog_preproc declaration) out into a
new file at frontends/verilog/preproc.h and included that where
necessary.

Finally, the patch adds a few tests in tests/various to check that we
are parsing everything correctly.
 2020-03-27 16:08:26 +00:00
Alberto Gonzalez
6040593994
Revert over-aggressive change to a more modest cleanup. 2020-03-27 09:46:40 +00:00
Peter Crozier
9a8a644ad1 Error duplicate declarations of a typedef name in the same scope. 2020-03-24 14:35:21 +00:00
Peter Crozier
ecc22f7fed Support module/package/interface/block scope for typedef names. 2020-03-23 20:07:22 +00:00
Peter Crozier
6cad865d12 Simplify was not being called for packages. Broke typedef enums. 2020-03-22 18:20:46 -07:00
Peter Crozier
c06eda2504 Build pkg_user_types before parsing in case of changes in the design. 2020-03-22 18:20:46 -07:00
Peter
0aaa36ca6d Clear pkg_user_types if no packages following a 'design -reset-vlog'. 2020-03-22 18:20:46 -07:00
Peter
14f32028ec Parser changes to support typedef. 2020-03-22 18:20:46 -07:00
Eddie Hung
f828cb5132
Merge pull request #1788 from YosysHQ/eddie/fix_ndebug 
Fix NDEBUG warnings
 2020-03-19 14:58:06 -07:00
Miodrag Milanović
d46259becd
Merge pull request #1787 from YosysHQ/mmicko/lexer_deps 
Add dependency to verilog_lexer.cc
 2020-03-19 18:24:40 +01:00
Miodrag Milanovic
dc75ed7dac Add one mode dependency 2020-03-19 16:53:40 +01:00
Eddie Hung
43092f063f Fix NDEBUG warnings 2020-03-19 08:48:39 -07:00
N. Engelhardt
b473264a06
Merge pull request #1775 from huaixv/asserts_locations 
Add precise locations for asserts
 2020-03-19 13:12:18 +01:00
Alberto Gonzalez
eb30d66d01
Clean up pseudo-private member usage in frontends/ast/ast.cc. 2020-03-19 07:29:00 +00:00
huaixv
cd82ccd258 Add precise locations for asserts 2020-03-19 10:22:07 +08:00
Eddie Hung
4555b5b819 kernel: more pass by const ref, more speedups 2020-03-18 11:21:53 -07:00
Alberto Gonzalez
6dd2024965
Add AST node source location information in a couple more parser rules. 2020-03-17 06:22:12 +00:00
Miodrag Milanović
569e834df2
Merge pull request #1759 from zeldin/constant_with_comment_redux 
refixed parsing of constant with comment between size and value
 2020-03-14 13:34:59 +02:00
Miodrag Milanović
faf4ee69de
Merge pull request #1754 from boqwxp/precise_locations 
Set AST node source location in more parser rules.
 2020-03-14 11:18:39 +02:00
Marcus Comstedt
5e94bf0291 refixed parsing of constant with comment between size and value 
The three parts of a based constant (size, base, digits) are now three
separate tokens, allowing the linear whitespace (including comments)
between them to be treated as normal inter-token whitespace.
 2020-03-11 18:21:44 +01:00
jiegec
7b679eecb3 Fix compilation for emcc 2020-03-11 22:09:24 +08:00
Eddie Hung
2d63bf5877 verilog: also set location for simple_behavioral_stmt 2020-03-10 10:29:24 -07:00
Alberto Gonzalez
da8270aa01
Set AST source locations in more parser rules. 2020-03-10 01:50:39 +00:00
Claire Wolf
a7cc4673c3 Fix partsel expr bit width handling and add test case 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-03-08 16:12:12 +01:00
Claire Wolf
d59da5a4e4 Fix bison warning for "pure-parser" option 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-03-03 08:41:55 -08:00
Claire Wolf
b597f85b13
Merge pull request #1718 from boqwxp/precise_locations 
Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.
 2020-03-03 08:38:32 -08:00
Claire Wolf
91892465e1
Merge pull request #1681 from YosysHQ/eddie/fix1663 
verilog: instead of modifying localparam size, extend init constant expr
 2020-03-03 08:34:31 -08:00
Eddie Hung
4f889b2f57
Merge pull request #1724 from YosysHQ/eddie/abc9_specify 
abc9: auto-generate *.lut/*.box files and arrival/required times from specify entries
 2020-03-02 12:32:27 -08:00
Eddie Hung
5bba9c3640 ast: fixes #1710; do not generate RTLIL for unreachable ternary 2020-02-27 16:55:55 -08:00