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yosys/frontends
Rupert Swarbrick 044ca9dde4 Add support for SystemVerilog-style `define to Verilog frontend
This patch should support things like

  `define foo(a, b = 3, c)   a+b+c

  `foo(1, ,2)

which will evaluate to 1+3+2. It also spots mistakes like

  `foo(1)

(the 3rd argument doesn't have a default value, so a call site is
required to set it).

Most of the patch is a simple parser for the format in preproc.cc, but
I've also taken the opportunity to wrap up the "name -> definition"
map in a type, rather than use multiple std::map's.

Since this type needs to be visible to code that touches defines, I've
pulled it (and the frontend_verilog_preproc declaration) out into a
new file at frontends/verilog/preproc.h and included that where
necessary.

Finally, the patch adds a few tests in tests/various to check that we
are parsing everything correctly.
2020-03-27 16:08:26 +00:00
..
aiger Fix NDEBUG warnings 2020-03-19 08:48:39 -07:00
ast Simplify was not being called for packages. Broke typedef enums. 2020-03-22 18:20:46 -07:00
blif Fix parsing of .cname BLIF statements 2019-10-16 09:06:57 +02:00
ilang read_ilang: do bounds checking on bit indices 2019-11-27 22:24:39 +01:00
json Update JSON front-end to process new attr/param encoding 2019-08-01 12:48:22 +02:00
liberty stoi -> atoi 2019-08-07 11:09:17 -07:00
rpc Fix compilation for emcc 2020-03-11 22:09:24 +08:00
verific Merge pull request from YosysHQ/clifford/verificnand 2020-01-30 19:55:53 +01:00
verilog Add support for SystemVerilog-style `define to Verilog frontend 2020-03-27 16:08:26 +00:00