280 commits

Author	SHA1	Message	Date
Clifford Wolf	26766da343	Add a paragraph about pre-defined macros to read_verilog help message	2017-07-21 14:34:53 +02:00
Clifford Wolf	8f8baccfde	Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand const reg"	2017-06-07 12:30:24 +02:00
Clifford Wolf	129984e115	Fix handling of Verilog ~& and ~| operators	2017-06-01 12:43:21 +02:00
Clifford Wolf	e91548b33e	Add support for localparam in module header	2017-04-30 17:20:30 +02:00
Clifford Wolf	f0db8ffdbc	Add support for `resetall compiler directive	2017-04-26 16:09:41 +02:00
Clifford Wolf	088f9c9cab	Fix verilog pre-processor for multi-level relative includes	2017-03-14 17:30:20 +01:00
Clifford Wolf	5b3b5ffc8c	Allow $anyconst, etc. in non-formal SV mode	2017-03-01 10:47:05 +01:00
Clifford Wolf	5f1d0b1024	Add $live and $fair cell types, add support for s_eventually keyword	2017-02-25 10:36:39 +01:00
Clifford Wolf	00dba4c197	Add support for SystemVerilog unique, unique0, and priority case	2017-02-23 16:33:19 +01:00
Clifford Wolf	34d4e72132	Added SystemVerilog support for ++ and --	2017-02-23 11:21:33 +01:00
Clifford Wolf	848062088c	Add checker support to verilog front-end	2017-02-09 13:51:44 +01:00
Clifford Wolf	ef4a28e112	Add SV "rand" and "const rand" support	2017-02-08 14:38:15 +01:00
Clifford Wolf	6abf79eb28	Further improve cover() support	2017-02-04 17:02:13 +01:00
Clifford Wolf	3928482a3c	Add $cover cell type and SVA cover() support	2017-02-04 14:14:26 +01:00
Clifford Wolf	fea528280b	Add "enum" and "typedef" lexer support	2017-01-17 17:33:52 +01:00
Clifford Wolf	3886669ab6	Added "verilog_defines" command	2016-12-15 17:49:28 +01:00
Clifford Wolf	ecdc22b06c	Added support for macros as include file names	2016-11-28 14:50:17 +01:00
Clifford Wolf	c7f6fb6e17	Bugfix in "read_verilog -D NAME=VAL" handling	2016-11-28 14:45:05 +01:00
Clifford Wolf	70d7a02cae	Added support for hierarchical defparams	2016-11-15 13:35:19 +01:00
Clifford Wolf	a926a6afc2	Remember global declarations and defines accross read_verilog calls	2016-11-15 12:42:43 +01:00
Clifford Wolf	bdc316db50	Added $anyseq cell type	2016-10-14 15:24:03 +02:00
Clifford Wolf	6f41e5277d	Removed $aconst cell type	2016-08-30 19:09:56 +02:00
Clifford Wolf	eae390ae17	Removed $predict again	2016-08-28 21:35:33 +02:00
Clifford Wolf	1276c87a56	Added read_verilog -norestrict -assume-asserts	2016-08-26 23:35:27 +02:00
Clifford Wolf	4be4969bae	Improved verilog parser errors	2016-08-25 11:44:37 +02:00
Clifford Wolf	cd18235f30	Added SV "restrict" keyword	2016-08-24 15:30:08 +02:00
Clifford Wolf	7f755dec75	Fixed bug in parsing real constants	2016-08-06 13:16:23 +02:00
Clifford Wolf	4056312987	Added $anyconst and $aconst	2016-07-27 15:41:22 +02:00
Clifford Wolf	a7b0769623	Added "read_verilog -dump_rtlil"	2016-07-27 15:40:17 +02:00
Clifford Wolf	5b944ef11b	Fixed a verilog parser memory leak	2016-07-25 16:37:58 +02:00
Clifford Wolf	7a67add95d	Fixed parsing of empty positional cell ports	2016-07-25 12:48:03 +02:00
Clifford Wolf	9aae1d1e8f	No tristate warning message for "read_verilog -lib"	2016-07-23 11:56:53 +02:00
Clifford Wolf	5c166e76e5	Added $initstate cell type and vlog function	2016-07-21 14:23:22 +02:00
Clifford Wolf	d7763634b6	After reading the SV spec, using non-standard predict() instead of expect()	2016-07-21 13:34:33 +02:00
Clifford Wolf	721f1f5ecf	Added basic support for $expect cells	2016-07-13 16:56:17 +02:00
Ruben Undheim	545bcb37e8	Allow defining input ports as "input logic" in SystemVerilog	2016-06-20 20:16:37 +02:00
Ruben Undheim	178ff3e7f6	Added support for SystemVerilog packages with localparam definitions	2016-06-18 10:53:55 +02:00
Clifford Wolf	060bf4819a	Small improvements in Verilog front-end docs	2016-05-20 16:21:35 +02:00
Clifford Wolf	0bc95f1e04	Added "yosys -D" feature	2016-04-21 23:28:37 +02:00
Clifford Wolf	5a09fa4553	Fixed handling of parameters and const functions in casex/casez pattern	2016-04-21 15:31:54 +02:00
Clifford Wolf	33c10350b2	Fixed Verilog parser fix and more similar improvements	2016-03-15 12:22:31 +01:00
Andrew Becker	81d4e9e7c1	Use left-recursive rule for cell_port_list in Verilog parser.	2016-03-15 12:03:40 +01:00
Clifford Wolf	35a6ad4cc1	Fixed typos in verilog_defaults help message	2016-03-10 11:14:51 +01:00
Clifford Wolf	34f2b84fb6	Fixed handling of parameters and localparams in functions	2015-11-11 10:54:35 +01:00
Clifford Wolf	5308c1e02a	Fixed bug in verilog parser	2015-10-15 15:19:23 +02:00
Clifford Wolf	f13e387321	SystemVerilog also has assume(), added implicit -D FORMAL	2015-10-13 14:21:20 +02:00
Clifford Wolf	ba4cce9f19	Added support for "parameter" and "localparam" in global context	2015-10-07 14:59:08 +02:00
Clifford Wolf	e2e092b144	Added read_verilog -nodpi	2015-09-23 08:23:38 +02:00
Clifford Wolf	b845b77f86	Fixed support for $write system task	2015-09-23 07:10:56 +02:00
Clifford Wolf	a3a13cce32	Fixed detection of "task foo(bar);" syntax error	2015-09-22 21:34:21 +02:00