410 commits

Author	SHA1	Message	Date
Emil J. Tywoniak	3b64de3762	fix $specrule port naming	2026-04-13 16:48:27 +02:00
nella	fc71719e6e	Rename csa_tree to arith_tree.	2026-04-13 12:48:05 +02:00
nella	0f61ba5299	Move csa after alumacc.	2026-04-13 12:48:05 +02:00
nella	b64b75db7a	Add csa to synth.	2026-04-13 12:48:05 +02:00
Emil J	86448c0001	Merge pull request #5655 from YosysHQ/emil/dffsr-sr-priority-undef ... Undefine set&reset behavior of $dffsr	2026-04-08 14:22:34 +00:00
Emil J. Tywoniak	0e7f7c826d	simcells: $dffsr and derivatives undefine S&R in logic tables	2026-03-19 19:27:30 +01:00
Lofty	c4cc53a72e	synth: fix after abc -fast removal	2026-03-18 17:59:58 +01:00
Robert O'Callahan	e87bb65956	Move Design::sort() calls out of opt and opt_clean passes into the synth passes that need them.	2026-01-23 01:14:35 +00:00
Emil J. Tywoniak	1edc32dcd0	opensta, sdc_expand: mark as experimental	2025-11-19 15:31:17 +01:00
Emil J. Tywoniak	85d2702ef6	opensta, sdc_expand: fix help	2025-11-19 15:20:50 +01:00
Emil J. Tywoniak	411fc149df	opensta: refactor default command	2025-11-19 15:20:50 +01:00
Emil J. Tywoniak	a5b6c3cc19	opensta, sdc_expand: more scratchpad	2025-11-19 15:20:50 +01:00
Emil J. Tywoniak	6846168db3	opensta: opensta.exe scratchpad variable	2025-11-19 15:20:50 +01:00
Emil J. Tywoniak	5acb77cab1	sdc_expand, opensta: typos	2025-11-19 15:20:50 +01:00
Emil J. Tywoniak	7bc88d5c40	sdc_expand: cleanup	2025-11-19 15:20:50 +01:00
Emil J. Tywoniak	793594bd59	sdc_expand: log header	2025-11-19 15:20:50 +01:00
Emil J. Tywoniak	7bed6ec658	opensta: quiet blackbox warning	2025-11-19 15:20:50 +01:00
Emil J. Tywoniak	0c4105d72c	opensta: quiet net width mismatch warning	2025-11-19 15:20:50 +01:00
Emil J. Tywoniak	bbf1e4bca2	sdc_expand, opensta: start	2025-11-19 15:20:50 +01:00
Emil J. Tywoniak	f47540b950	techlibs: remove cells.lib	2025-11-14 15:40:14 +01:00
Ethan Sifferman	d5beb65d30	added SIMLIB_VERILATOR_COMPAT	2025-10-01 10:19:25 -07:00
Ethan Sifferman	0eb93c80e6	added ifndef SIMLIB_NOCONNECT	2025-09-24 20:50:47 -07:00
Emil J. Tywoniak	d30f7847d8	techmap: map $alu to $fa instead of relying on extract_fa	2025-09-23 17:05:12 +02:00
Emil J	a78eb9e151	Merge pull request #5315 from YosysHQ/emil/write_rtlil-no-sort ... write_rtlil: don't sort	2025-09-22 11:14:39 +02:00
Jannis Harder	1251e92e3a	Add $input_port and $connect cell types	2025-09-17 13:56:46 +02:00
Emil J. Tywoniak	73747f6928	read_verilog: add -relativeshare for synthesis reproducibility testing	2025-09-16 15:47:35 +02:00
Robert O'Callahan	c7df6954b9	Remove .c_str() from stringf parameters	2025-09-01 23:34:42 +00:00
Martin Povišer	415b7d3f65	Drop experimental label off synth -hieropt	2025-07-17 12:02:44 +02:00
Martin Povišer	22a44e4333	Start opt_hier	2025-07-05 16:45:52 +02:00
Scott Ashcroft	04bbd4e7e2	Make all vector-size related integer params in $print sim model signed ... This fixes iverilog crashes on 32-bit, similar to 95944eb for $mem.	2025-03-25 13:08:49 +00:00
Martin Povišer	6da543a61a	Merge pull request #4818 from povik/macc_v2 ... Add `$macc_v2`	2025-03-12 22:55:40 +01:00
Martin Povišer	557047fe1e	opt_clean, simplemap: Add $buf handling	2025-03-07 16:08:38 +01:00
Martin Povišer	6c76dcec3e	macc_v2: Fix v2 omissions	2025-01-27 13:08:44 +01:00
Martin Povišer	3184b335da	macc_v2: Fix language constructs in simlib model	2025-01-24 13:22:30 +01:00
Martin Povišer	1e8aa56f7f	macc_v2: Init simlib model	2025-01-24 12:38:03 +01:00
Emil J	61a6567b9f	Merge pull request #4789 from YosysHQ/emil/sklansky-adder ... Add a Sklansky option for `$lcu` mapping	2024-12-03 11:33:13 +01:00
Emil J. Tywoniak	fe64a714a9	techmap: add a Sklansky option for $lcu mapping	2024-12-02 11:34:58 +01:00
Emil J. Tywoniak	ebd7f2b366	techlibs: add _TECHMAP_DO_ to Han-Carlson adder	2024-12-02 09:54:24 +01:00
Emil J. Tywoniak	4bf3677640	techmap: set Han-Carlson adder priority consistent with Kogge-Stone	2024-11-28 23:54:00 +01:00
Emil J. Tywoniak	6c78bd3637	techmap: add a Han-Carlson option for $lcu mapping	2024-11-28 15:33:21 +01:00
Krystine Sherwin	27b8b4e81e	Docs: Fix missing groups ... $lut and $sop were missed in the rebase, and $buf is new to main since the last rebase.	2024-10-15 11:08:30 +13:00
Krystine Sherwin	1513366f21	Docs: Adding mux cell descriptions ... Also making ver2 cell descriptions consistently spaced.	2024-10-15 07:37:34 +13:00
Krystine Sherwin	dfe803b5c6	Docs: Comments from @jix ... - Unswap shift/shiftx - Add brief overview to cell lib - Clarify $div cell B input - Clarify unary operators - What is $modfloor	2024-10-15 07:37:20 +13:00
Krystine Sherwin	4d84d7e69f	simlib.v: Add x-output tag ... Also a few extra cell help texts.	2024-10-15 07:35:41 +13:00
Krystine Sherwin	ed92374263	simlib.v: Update case equality operators to v2 ... Also tag as x-aware cells and add titles.	2024-10-15 07:35:41 +13:00
Krystine Sherwin	b1025dbaa6	cellhelp.py: Cells can have tags ... Tags are added to the list of properties when exporting to `cells.json`.	2024-10-15 07:35:41 +13:00
Krystine Sherwin	f70a66f5b3	Docs: Assert cell has group ... Explicitly assign $_TBUF_ to `gate_other` and remove catch if a cell has no group.	2024-10-15 07:35:40 +13:00
Krystine Sherwin	5c4f7b4deb	Docs: $eqx aka case equality	2024-10-15 07:35:40 +13:00
Krystine Sherwin	596d914ead	simcells: Apply group tags	2024-10-15 07:35:40 +13:00
Krystine Sherwin	78b9dbd4ea	Docs: Assign remaining word cells to groups ... Move todos to correct place. Add todo for x-prop cells.	2024-10-15 07:35:40 +13:00