Eddie Hung
43616e1414
Update Makefile too
2019-07-18 14:51:55 -07:00
Eddie Hung
b97fe6e866
Work in progress for renaming labels/options in synth_xilinx
2019-07-18 14:20:43 -07:00
David Shah
9cb0456b6f
Merge pull request #1208 from ZirconiumX/intel_cleanups
...
Assorted synth_intel cleanups from @bwidawsk
2019-07-18 19:04:28 +01:00
Dan Ravensloft
0c999ac2c4
synth_intel: Use stringf
2019-07-18 19:02:23 +01:00
Dan Ravensloft
50f5e29724
synth_intel: s/not family/no family/
2019-07-18 17:28:21 +01:00
Ben Widawsky
999811572a
intel_synth: Fix help message
...
cyclonev has been a "supported" family since the initial commit. The old
commit message suggested to use a10gx which is incorrect.
Aside from the obvious lack of functional change due to this just being
a help message, users who were previously using "a10gx" for "cyclonev" will
also have no functional change by using "cyclonev" instead.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2019-07-18 17:06:25 +01:00
Ben Widawsky
f950a7a75d
intel_synth: Small code cleanup to remove if ladder
...
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2019-07-18 17:06:12 +01:00
Ben Widawsky
809b94a67b
intel_synth: Make family explicit and match
...
The help and code default to MAX10 for the family, however the couple of
if ladders defaulted to cycloneive. Fix this inconsistency and the next
patch will clean it up.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2019-07-18 17:06:03 +01:00
Ben Widawsky
060e77c09b
intel_synth: Minor code cleanups
...
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2019-07-18 17:05:54 +01:00
Dan Ravensloft
c78ab8ebc5
synth_intel: rename for consistency with #1184
...
Also fix a typo in the help message.
2019-07-18 16:46:21 +01:00
Clifford Wolf
e66e8fb59d
Merge pull request #1184 from whitequark/synth-better-labels
...
synth_{ice40,ecp5}: more sensible pass label naming
2019-07-18 15:34:28 +02:00
David Shah
82153059a1
Merge pull request #1204 from smunaut/fix_1187
...
ice40: Adapt the relut process passes to the new $lut/SB_LUT4 port map
2019-07-17 07:55:26 +01:00
Sylvain Munaut
f28e38de99
ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port map
...
The new mapping introduced in 437fec0d88Fixes #1187
(Diagnosis of the issue by @daveshah1 on IRC)
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2019-07-16 23:57:15 +02:00
whitequark
698ab9beee
synth_ecp5: rename dram to lutram everywhere.
2019-07-16 20:45:12 +00:00
whitequark
ba099bfe9b
synth_{ice40,ecp5}: more sensible pass label naming.
2019-07-16 20:41:51 +00:00
Eddie Hung
7a58ee78dc
gen_lut to return correctly sized LUT mask
2019-07-16 12:45:29 -07:00
Eddie Hung
ba8ccbdea8
Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fix
...
abc9/ice40: encapsulate SB_CARRY+SB_LUT4 into one box
2019-07-16 08:52:14 -07:00
Eddie Hung
5fb27c071b
$__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark
2019-07-15 12:03:51 -07:00
Eddie Hung
d032198fac
ice40_opt to $__ICE40_CARRY_LUT4 into $lut not SB_LUT
2019-07-13 01:11:00 -07:00
Clifford Wolf
463f710066
Merge pull request #1183 from whitequark/ice40-always-relut
...
synth_ice40: switch -relut to be always on
2019-07-12 10:48:00 +02:00
Eddie Hung
7a912f22b2
Use Const::from_string() not its constructor...
2019-07-12 01:32:10 -07:00
Eddie Hung
28274dfb09
Off by one
2019-07-12 01:17:53 -07:00
Eddie Hung
e0e5d7d68e
Fix spacing
2019-07-12 01:15:22 -07:00
Eddie Hung
4de03bd5e6
Remove double push
2019-07-12 01:08:48 -07:00
Eddie Hung
62ac5ebd02
Map to and from this box if -abc9
2019-07-12 00:53:01 -07:00
Eddie Hung
0f5bddcd79
ice40_opt to handle this box and opt back to SB_LUT4
2019-07-12 00:52:31 -07:00
Eddie Hung
a79ff2501e
Add new box to cells_sim.v
2019-07-12 00:52:19 -07:00
Eddie Hung
c6e16e1334
_ABC macro will map and unmap to this new box
2019-07-12 00:51:37 -07:00
Eddie Hung
fc3d74616f
Combine SB_CARRY+SB_LUT into one $__ICE40_CARRY_LUT4 box
2019-07-12 00:50:42 -07:00
Eddie Hung
1c9f3fadb9
Add Tsu offset to boxes, and comments
2019-07-11 17:17:26 -07:00
Eddie Hung
d386177e6d
ABC doesn't like negative delays in flop boxes...
2019-07-11 17:09:17 -07:00
Eddie Hung
3ef927647c
Fix FDCE_1 box
2019-07-11 14:25:47 -07:00
Eddie Hung
1ada568134
Revert "$pastQ should be first input"
...
This reverts commit 8f9d529929
2019-07-11 14:23:45 -07:00
Eddie Hung
854333f2af
Propagate INIT attr
2019-07-11 13:55:47 -07:00
Eddie Hung
8f9d529929
$pastQ should be first input
2019-07-11 13:54:40 -07:00
Eddie Hung
021f8e5492
Fix typo
2019-07-11 13:23:07 -07:00
whitequark
b700a4b1c5
synth_ice40: switch -relut to be always on.
2019-07-11 20:18:41 +00:00
whitequark
a8c5f7f41e
synth_ice40: fix help text typo. NFC.
2019-07-11 20:18:41 +00:00
Eddie Hung
19c1c3cfa3
Merge pull request #1182 from koriakin/xc6s-bram
...
synth_xilinx: Initial Spartan 6 block RAM inference support.
2019-07-11 12:55:35 -07:00
Marcin Kościelnicki
a9efacd01d
xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Vivado.
2019-07-11 21:13:12 +02:00
Eddie Hung
8fef4c3594
Simplify to $__ABC_ASYNC box
2019-07-11 10:52:33 -07:00
Eddie Hung
93fbd56db1
$__ABC_FD_ASYNC_MUX.Q -> Y
2019-07-11 10:25:59 -07:00
Marcin Kościelnicki
ce250b341c
synth_xilinx: Initial Spartan 6 block RAM inference support.
2019-07-11 14:45:48 +02:00
Eddie Hung
d357431df1
Restore from master
2019-07-10 22:54:39 -07:00
Eddie Hung
f984e0cb34
Another typo
2019-07-10 22:33:35 -07:00
Eddie Hung
ea6ffea2cd
Fix clk_pol for FD*_1
2019-07-10 20:10:20 -07:00
Eddie Hung
7899a06ed6
Another typo
2019-07-10 19:59:24 -07:00
Eddie Hung
ad35b509de
Another typo
2019-07-10 19:05:53 -07:00
Eddie Hung
f3511e4f93
Use \$currQ
2019-07-10 19:01:13 -07:00
Eddie Hung
f030be3f1c
Preserve all parameters, plus some extra ones for clk/en polarity
2019-07-10 18:57:11 -07:00
