2092 commits

Author	SHA1	Message	Date
Eddie Hung	8691596d19	Revert "Try way that doesn't involve creating a new wire" ... This reverts commit 2f427acc9e.	2019-08-22 16:16:34 -07:00
Eddie Hung	5ff75b1cdc	Try way that doesn't involve creating a new wire	2019-08-22 16:16:34 -07:00
Eddie Hung	e1fff34dde	If d_bit already in sigbit_chain_next, create extra wire	2019-08-22 16:16:34 -07:00
Eddie Hung	6e8fda8bf0	Add doc	2019-08-22 11:52:24 -07:00
Eddie Hung	cabadb85e2	Add copyright	2019-08-22 11:25:19 -07:00
Eddie Hung	36d94caec1	Remove shregmap -tech xilinx additions	2019-08-22 11:22:09 -07:00
Eddie Hung	9f3ed1726e	pmgen to also iterate over all module ports	2019-08-22 11:15:16 -07:00
Eddie Hung	74bd190d3b	Remove output_bits	2019-08-22 11:14:59 -07:00
Eddie Hung	231ddbf95c	Forgot to set ud_variable.minlen	2019-08-22 11:02:17 -07:00
Eddie Hung	61639d5387	Do not run xilinx_srl_pm in fixed loop	2019-08-22 10:51:04 -07:00
Eddie Hung	7188972645	Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl	2019-08-22 10:32:54 -07:00
Eddie Hung	d0b2973413	Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl	2019-08-22 10:32:06 -07:00
Eddie Hung	b800059fc1	Merge pull request #1317 from YosysHQ/eddie/opt_expr_shiftx ... opt_expr to trim A port of $shiftx/$shift	2019-08-22 10:31:27 -07:00
Eddie Hung	9245f0d3f5	Copy-paste typo	2019-08-22 08:43:44 -07:00
Eddie Hung	6f971470f8	Respect opt_expr -keepdc as per @cliffordwolf	2019-08-22 08:37:27 -07:00
Eddie Hung	379f33af54	Handle $shift and Y_WIDTH > 1 as per @cliffordwolf	2019-08-22 08:22:23 -07:00
Eddie Hung	9e31f01b34	Add cover()	2019-08-22 08:06:24 -07:00
Eddie Hung	d0ffe7544c	Canonical form	2019-08-22 08:05:01 -07:00
Eddie Hung	d3a212ff91	opt_expr to trim A port of $shiftx if Y_WIDTH == 1	2019-08-21 21:53:55 -07:00
Eddie Hung	7d02d17b16	Reuse var	2019-08-21 19:18:40 -07:00
Eddie Hung	5c8344363f	Revert "Trim shiftx_width when upper bits are 1'bx" ... This reverts commit 7e7965ca7b.	2019-08-21 19:18:27 -07:00
Eddie Hung	c7859531c2	opt_expr to trim A port of $shiftx if Y_WIDTH == 1	2019-08-21 19:18:05 -07:00
Eddie Hung	7e7965ca7b	Trim shiftx_width when upper bits are 1'bx	2019-08-21 18:43:17 -07:00
Eddie Hung	ed7be3e6b6	Add comment	2019-08-21 17:36:38 -07:00
Eddie Hung	15188033da	Add variable length support to xilinx_srl	2019-08-21 17:34:40 -07:00
Eddie Hung	6d76ae4c65	Rename pattern to fixed	2019-08-21 15:46:58 -07:00
Eddie Hung	b0a3b430bf	attribute -> attr	2019-08-21 15:44:07 -07:00
Eddie Hung	61b4d7ae13	Use Cell::has_keep_attribute()	2019-08-21 15:41:46 -07:00
Eddie Hung	6fa9e03e4c	xilinx_srl to support FDRE and FDRE_1	2019-08-21 15:35:29 -07:00
Eddie Hung	3c8e8521a6	Fix polarity of EN_POL	2019-08-21 14:42:11 -07:00
Eddie Hung	a980f0d4be	Add CLKPOL == 0	2019-08-21 14:35:40 -07:00
Eddie Hung	1c7d721558	Reject if not minlen from inside pattern matcher	2019-08-21 14:26:24 -07:00
Eddie Hung	cab2bd083e	Get wire via SigBit	2019-08-21 13:47:47 -07:00
Eddie Hung	52fea5b658	Respect \keep on cells or wires	2019-08-21 13:42:03 -07:00
Eddie Hung	5ce0c31d0e	Add init support	2019-08-21 13:05:10 -07:00
Eddie Hung	df53fe12e7	Fix spacing	2019-08-21 12:54:11 -07:00
Eddie Hung	0250712486	Initial progress on xilinx_srl	2019-08-21 12:50:49 -07:00
Miodrag Milanovic	948b6f91a1	Fix test_pmgen deps	2019-08-21 17:00:24 +02:00
Clifford Wolf	7d8db1c053	Merge pull request #1314 from YosysHQ/eddie/fix_techmap ... techmap -max_iter to apply to each module individually	2019-08-21 09:12:56 +02:00
Eddie Hung	9b9d759451	Fix copy-paste typo	2019-08-20 20:18:51 -07:00
Eddie Hung	fe61dcce8b	Grammar	2019-08-20 20:05:51 -07:00
Eddie Hung	193eae0c84	techmap -max_iter to apply to each module individually	2019-08-20 19:50:20 -07:00
Eddie Hung	14c03861b6	Merge pull request #1304 from YosysHQ/eddie/abc9_refactor ... Refactor abc9 to use port attributes, not module attributes	2019-08-20 11:59:31 -07:00
Clifford Wolf	d0117d7d12	Merge branch 'master' into clifford/pmgen	2019-08-20 11:39:23 +02:00
whitequark	749ff864aa	Merge pull request #1309 from whitequark/proc_clean-fix-1268 ... proc_clean: fix order of switch insertion	2019-08-20 00:45:41 +00:00
Eddie Hung	7e010834eb	Fix typo	2019-08-19 10:41:18 -07:00
Eddie Hung	f42ba811b6	ID({A,B,Y}) -> ID::{A,B,Y} for opt_share.cc	2019-08-19 10:11:47 -07:00
Eddie Hung	d81a090d89	Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro	2019-08-19 09:56:17 -07:00
whitequark	4a942ba7b9	proc_clean: fix order of switch insertion. ... Fixes #1268.	2019-08-19 16:44:23 +00:00
Clifford Wolf	1e3dd0a2da	Merge branch 'master' of github.com:YosysHQ/yosys into clifford/pmgen	2019-08-19 13:04:06 +02:00