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Author SHA1 Message Date
whitequark
ae409d4d81
Merge pull request #2012 from whitequark/fix-wasi-abc-build 
Fix WASI builds with abc enabled
 2020-05-05 14:03:40 +00:00
Eddie Hung
5fa06e4894
Merge pull request #2026 from YosysHQ/eddie/scratchpad_abc9_W 
synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpad
 2020-05-05 06:49:36 -07:00
Eddie Hung
7a62ee57b4
Merge pull request #2024 from YosysHQ/eddie/primitive_src 
verilog: set src attribute for primitives
 2020-05-05 06:49:18 -07:00
Eddie Hung
99aff5a0f9
Merge pull request #2023 from YosysHQ/eddie/specify_src 
verilog: fix specify src attribute
 2020-05-05 06:49:06 -07:00
whitequark
66d0ed2bcc ast/simplify: don't bitblast async ROMs declared as logic. 
Fixes #2020.
 2020-05-05 04:16:59 +00:00
Eddie Hung
e936ac61ea ast: swap range regardless of range_left >= 0 2020-05-04 12:18:20 -07:00
Eddie Hung
2e911bc806 test: add failing test 2020-05-04 12:18:02 -07:00
Eddie Hung
e6b55e8b38 synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpad 2020-05-04 11:44:00 -07:00
Eddie Hung
eb5eb60fd4 verilog: fix specify src attribute 2020-05-04 10:53:06 -07:00
Eddie Hung
22bf22fab4 frontend: cleanup to use more ID::*, more dict<> instead of map<> 2020-05-04 10:48:37 -07:00
Eddie Hung
eca9fc01a7 verilog: set src attribute for primitives 2020-05-04 10:22:05 -07:00
Eddie Hung
ad8e7878f6 tests: add tests for primitives' src 2020-05-04 10:21:47 -07:00
Eddie Hung
584780d776
Merge pull request #1996 from boqwxp/rtlil_source_locations 
frontend: Include complete source location instead of just `location.first_line` in `frontends/ast/genrtlil.cc`.
 2020-05-04 08:58:50 -07:00
whitequark
d1c8837572
Merge pull request #2000 from whitequark/log_error-trap 
kernel: Trap in `log_error()` when a debugger is attached
 2020-05-03 16:19:42 +00:00
whitequark
e9f2d3f009 kernel: Trap in log_error() when a debugger is attached. 
The workflow of debugging fatal pass errors in Yosys is flawed in
three ways:
 1. Running Yosys under a debugger is sufficient for the debugger
    to catch some fatal errors (segfaults, aborts, STL exceptions)
    but not others (`log_error()`, `log_cmd_error()`). This is
    neither obvious nor easy to remember.
 2. To catch Yosys-specific fatal errors, it is necessary to set
    a breakpoint at `logv_error_with_prefix()`, or at least,
    `logv_error()`. This is neither obvious nor easy to remember,
    and GDB's autocomplete takes many seconds to suggest function
    names due to the large amount of symbols in Yosys.
 3. If a breakpoint is not set and Yosys encounters with such
    a fatal error, the process terminates. When debugging a crash
    that takes a long time to reproduce (or a nondeterministic crash)
    this can waste a significant amount of time.

To solve this problem, add a macro `YS_DEBUGTRAP` that acts as a hard
breakpoint (if available), and a macro `YS_DEBUGTRAP_IF_DEBUGGING`
that acts as a hard breakpoint only if debugger is present.

Then, use `YS_DEBUGTRAP_IF_DEBUGGING` in `logv_error_with_prefix()`
to obviate the need for a breakpoint on nearly every platform.

Co-Authored-By: Alberto Gonzalez <boqwxp@airmail.cc>
 2020-05-03 12:02:34 +00:00
Claire Wolf
5c82c19b4b
Merge pull request #2014 from YosysHQ/claire/fixoptalu 
Fix the other "opt_expr -fine" bug introduced in 213a89558
 2020-05-03 11:56:29 +02:00
Eddie Hung
db13852ed6 test: add test for #2014 2020-05-02 14:22:37 -07:00
Eddie Hung
7360155459
Merge pull request #2013 from YosysHQ/eddie/aiger_fixes 
aiger: fixes for ports that have start_offset != 0
 2020-05-02 14:16:10 -07:00
Claire Wolf
2285cf1219 Fix the other "opt_expr -fine" bug introduced in 213a89558 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-05-02 21:50:43 +02:00
Claire Wolf
885deb4e88 Fix the other "opt_expr -fine" bug introduced in 213a89558 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-05-02 21:34:24 +02:00
Eddie Hung
da7da44919 abc9_ops: -reintegrate to be sensitive to start_offset too 2020-05-02 11:19:04 -07:00
Eddie Hung
2e78daf1ca tests: aiger test for wire->start_offset != 0 2020-05-02 10:00:32 -07:00
Eddie Hung
a0afa1787e aiger: fixes for ports that have start_offset != 0 2020-05-02 10:00:32 -07:00
Claire Wolf
c3e5a070ea Add plusargs for output files in test_autotb output 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-05-02 11:21:01 +02:00
Claire Wolf
f38d76efbf Bugfix in partsel.v signed indices test cases 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-05-02 11:21:01 +02:00
Claire Wolf
88185f8959 Fix handling of signed indices in bit slices 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-05-02 11:21:01 +02:00
Claire Wolf
749c2ff84a Add tests based on the test case from #1990 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-05-02 11:21:01 +02:00
Claire Wolf
589ed2d970 Add AST_SELFSZ and improve handling of bit slices 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-05-02 11:21:01 +02:00
Claire Wolf
bbbce0d1c5 Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset, fixes #1990 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-05-02 11:21:01 +02:00
Claire Wolf
ca3fc3c882
Merge pull request #2010 from YosysHQ/claire/fixopt 
Fix "opt_expr -fine" bug introduced in 213a89558
 2020-05-02 11:20:02 +02:00
whitequark
ff7a8d0e1e Update ABC to include WASI support fixes. 2020-05-02 00:18:33 +00:00
whitequark
b36060cc20 Fix WASI builds with abc enabled. 
This PR works around #2011.
 2020-05-01 23:57:35 +00:00
whitequark
bbde241942
Merge pull request #2001 from whitequark/wasi 
Add WASI platform support
 2020-05-01 21:28:20 +00:00
Eddie Hung
7f9ecddb7f Add testcase for #2010 2020-05-01 14:07:33 -07:00
Claire Wolf
8ee32adac3 Fix "opt_expr -fine" bug introduced in 213a89558 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-05-01 20:12:16 +02:00
Claire Wolf
667f38fe53
Merge pull request #1997 from whitequark/document-ootb 
Explain how to do out-of-tree builds in README
 2020-05-01 15:35:33 +02:00
Claire Wolf
d047ca8b11
Merge pull request #1981 from YosysHQ/claire/fix1837 
Clear current_scope when done with RTLIL generation
 2020-05-01 14:58:41 +02:00
Alberto Gonzalez
b0268b1311
frontend: Include complete source location instead of just location.first_line in frontends/ast/genrtlil.cc. 2020-05-01 07:17:27 +00:00
whitequark
b43c282e4e Add WASI platform support. 
This includes the following significant changes:
  * Patching ezsat and minisat to disable resource limiting code
    on WASM/WASI, since the POSIX functions they use are unavailable.
  * Adding a new definition, YOSYS_DISABLE_SPAWN, present if platform
    does not support spawning subprocesses (i.e. Emscripten or WASI).
    This definition hides the definition of `run_command()`.
  * Adding a new Makefile flag, DISABLE_SPAWN, present in the same
    condition. This flag disables all passes that require spawning
    subprocesses for their function.
 2020-04-30 18:56:25 +00:00
Eddie Hung
bc380b0b56
Merge pull request #1999 from YosysHQ/eddie/verific_enum_again 
verific: recover wiretype/enum attr as part of import_attributes()
 2020-04-30 09:07:02 -07:00
whitequark
33c9c04561
Merge pull request #2008 from whitequark/editorconfig-abc 
Fix .editorconfig to not break abc
 2020-04-30 15:53:27 +00:00
Eddie Hung
5017ff4a97 verific: ignore anonymous enums 2020-04-30 07:48:47 -07:00
whitequark
adeed6f730 Fix .editorconfig to not break abc. 2020-04-30 02:22:37 +00:00
Eddie Hung
97bfe65d3a verific: support VHDL enums too 2020-04-27 15:17:13 -07:00
Eddie Hung
a66200ed1d
Merge pull request #1946 from YosysHQ/eddie/yosyshq_abc 
abc: use YosysHQ/abc instead of upstream berkeley-abc/abc
 2020-04-27 13:48:50 -07:00
Eddie Hung
c34d57de2e Update CHANGELOG and manual for departure from upstream 2020-04-27 12:08:45 -07:00
Eddie Hung
a3fa9fd6e9 abc: use YosysHQ/abc instead of upstream berkeley-abc/abc 
Enabling modifications
 2020-04-27 12:03:40 -07:00
Eddie Hung
eabc00de8b
Merge pull request #1992 from YosysHQ/eddie/bugpoint_help 
bugpoint: improve help text
 2020-04-27 11:12:17 -07:00
Vamsi K Vytla
adb483ddfd frontends/json/jsonparse.cc: Like the upto field read_json can also read the signedness of a wire 2020-04-27 10:36:18 -07:00
Vamsi K Vytla
5f9cd2e2f6 Preserve 'signed'-ness of a verilog wire through RTLIL 
As per suggestion made in https://github.com/YosysHQ/yosys/pull/1987, now:

RTLIL::wire holds an is_signed field.
This is exported in JSON backend
This is exported via dump_rtlil command
This is read in via ilang_parser
 2020-04-27 09:44:24 -07:00