160 commits

Author	SHA1	Message	Date
Clifford Wolf	3d27c1cc80	Merge pull request #513 from udif/pr_reg_wire_error ... Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test)	2018-08-15 13:35:41 +02:00
Udi Finkelstein	8b7580b0a1	Detect illegal port declaration, e.g input/output/inout keyword must be the first.	2018-06-06 22:27:25 +03:00
Udi Finkelstein	73d426bc87	Modified errors into warnings ... No longer false warnings for memories and assertions	2018-06-05 18:03:22 +03:00
Clifford Wolf	2d7f3123f0	Add statement labels for immediate assertions ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-04-13 11:52:28 +02:00
Clifford Wolf	66ffc99695	Allow "property" in immediate assertions ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-04-12 14:28:28 +02:00
Clifford Wolf	5ea2c53604	Add read_verilog anyseq/anyconst/allseq/allconst attribute support ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-04-06 14:35:11 +02:00
Udi Finkelstein	6378e2cd46	First draft of Verilog parser support for specify blocks and parameters. ... The only functionality of this code at the moment is to accept correct specify syntax and ignore it. No part of the specify block is added to the AST	2018-03-27 14:34:00 +02:00
Udi Finkelstein	2b9c75f8e3	This PR should be the base for discussion, do not merge it yet! ... It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements. What it DOES'T do: Detect registers connected to output ports of instances. Where it FAILS: memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals. You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines)	2018-03-11 23:09:34 +02:00
Clifford Wolf	eb67a7532b	Add $allconst and $allseq cell types ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-02-23 13:14:47 +01:00
Clifford Wolf	777f2881d8	Add Verilog "automatic" keyword (ignored in synthesis)	2017-11-23 08:51:38 +01:00
Clifford Wolf	5b6e52118c	Accept real-valued delay values	2017-11-18 10:01:30 +01:00
Udi Finkelstein	72a08eca3d	Resolved classical Bison IF/THEN/ELSE shift/reduce conflict using the textbook solution ... (Oreilly 'Flex & Bison' page 189)	2017-09-30 06:39:07 +03:00
Clifford Wolf	2cc09161ff	Fix ignoring of simulation timings so that invalid module parameters cause syntax errors	2017-09-26 01:52:59 +02:00
Clifford Wolf	8f8baccfde	Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand const reg"	2017-06-07 12:30:24 +02:00
Clifford Wolf	129984e115	Fix handling of Verilog ~& and ~| operators	2017-06-01 12:43:21 +02:00
Clifford Wolf	e91548b33e	Add support for localparam in module header	2017-04-30 17:20:30 +02:00
Clifford Wolf	5b3b5ffc8c	Allow $anyconst, etc. in non-formal SV mode	2017-03-01 10:47:05 +01:00
Clifford Wolf	5f1d0b1024	Add $live and $fair cell types, add support for s_eventually keyword	2017-02-25 10:36:39 +01:00
Clifford Wolf	00dba4c197	Add support for SystemVerilog unique, unique0, and priority case	2017-02-23 16:33:19 +01:00
Clifford Wolf	34d4e72132	Added SystemVerilog support for ++ and --	2017-02-23 11:21:33 +01:00
Clifford Wolf	848062088c	Add checker support to verilog front-end	2017-02-09 13:51:44 +01:00
Clifford Wolf	ef4a28e112	Add SV "rand" and "const rand" support	2017-02-08 14:38:15 +01:00
Clifford Wolf	6abf79eb28	Further improve cover() support	2017-02-04 17:02:13 +01:00
Clifford Wolf	3928482a3c	Add $cover cell type and SVA cover() support	2017-02-04 14:14:26 +01:00
Clifford Wolf	fea528280b	Add "enum" and "typedef" lexer support	2017-01-17 17:33:52 +01:00
Clifford Wolf	70d7a02cae	Added support for hierarchical defparams	2016-11-15 13:35:19 +01:00
Clifford Wolf	bdc316db50	Added $anyseq cell type	2016-10-14 15:24:03 +02:00
Clifford Wolf	6f41e5277d	Removed $aconst cell type	2016-08-30 19:09:56 +02:00
Clifford Wolf	eae390ae17	Removed $predict again	2016-08-28 21:35:33 +02:00
Clifford Wolf	1276c87a56	Added read_verilog -norestrict -assume-asserts	2016-08-26 23:35:27 +02:00
Clifford Wolf	4be4969bae	Improved verilog parser errors	2016-08-25 11:44:37 +02:00
Clifford Wolf	7f755dec75	Fixed bug in parsing real constants	2016-08-06 13:16:23 +02:00
Clifford Wolf	4056312987	Added $anyconst and $aconst	2016-07-27 15:41:22 +02:00
Clifford Wolf	5b944ef11b	Fixed a verilog parser memory leak	2016-07-25 16:37:58 +02:00
Clifford Wolf	7a67add95d	Fixed parsing of empty positional cell ports	2016-07-25 12:48:03 +02:00
Clifford Wolf	9aae1d1e8f	No tristate warning message for "read_verilog -lib"	2016-07-23 11:56:53 +02:00
Clifford Wolf	5c166e76e5	Added $initstate cell type and vlog function	2016-07-21 14:23:22 +02:00
Clifford Wolf	d7763634b6	After reading the SV spec, using non-standard predict() instead of expect()	2016-07-21 13:34:33 +02:00
Clifford Wolf	721f1f5ecf	Added basic support for $expect cells	2016-07-13 16:56:17 +02:00
Ruben Undheim	545bcb37e8	Allow defining input ports as "input logic" in SystemVerilog	2016-06-20 20:16:37 +02:00
Ruben Undheim	178ff3e7f6	Added support for SystemVerilog packages with localparam definitions	2016-06-18 10:53:55 +02:00
Clifford Wolf	5a09fa4553	Fixed handling of parameters and const functions in casex/casez pattern	2016-04-21 15:31:54 +02:00
Clifford Wolf	33c10350b2	Fixed Verilog parser fix and more similar improvements	2016-03-15 12:22:31 +01:00
Andrew Becker	81d4e9e7c1	Use left-recursive rule for cell_port_list in Verilog parser.	2016-03-15 12:03:40 +01:00
Clifford Wolf	34f2b84fb6	Fixed handling of parameters and localparams in functions	2015-11-11 10:54:35 +01:00
Clifford Wolf	5308c1e02a	Fixed bug in verilog parser	2015-10-15 15:19:23 +02:00
Clifford Wolf	ba4cce9f19	Added support for "parameter" and "localparam" in global context	2015-10-07 14:59:08 +02:00
Clifford Wolf	a3a13cce32	Fixed detection of "task foo(bar);" syntax error	2015-09-22 21:34:21 +02:00
Clifford Wolf	e4ef000b70	Adjust makefiles to work with out-of-tree builds ... This is based on work done by Larry Doolittle	2015-08-12 15:04:44 +02:00
Clifford Wolf	6c84341f22	Fixed trailing whitespaces	2015-07-02 11:14:30 +02:00