Add comments in setup-build-env/action.yml for where to document prereqs (and the separation between build/run and test).
Add some initial (very basic) text for `test_suites.rst`, listing prereqs and how to run the tests (with subsections for the different optional tests, which is currently docs, functional and unit).
Add sphinx-inline-tabs, use it for tidying up prereq instructions based on OS/platform (mostly helpful in the test suites doc where there are multiple sections split by OS).
Also fixes some single backticks that should be double backtick.
Allows files to be cleaned with `make clean`, without which it breaks out-of-tree builds if an in-tree build has previously run and subsequently cleaned.
- add `uv` to dependencies: saves builder(s) from manually having to manage a venv for python build dependencies
- when building wheels, pip automatically creates the environment with those dependencies, so no need for uv
- when running simply `make ENABLE_PYOSYS=1`, this is not the case. people attempting to `pip3 install --upgrade pybind11 cxxheaderparser` to add it to their system packages will be met with a scare message about "breaking system packages"
- update installation instructions to drop boost and add uv instead
- update ci scripts to use `macos-15[-intel]` (`macos-13` sunset in early december)
For these primitives, Gowin decided to use a different option for
describing ports—directly in the module header, i.e.
``` verilog
module ADC(input CLK);
```
instead of
``` verilog
module ADC(CLK);
input CLK;
```
Since this one-time parser becomes too confusing, it is easier to simply
add ADC descriptions as they are from a separate file, especially since
these primitives are only available in the GW5A series.
Test:
``` shell
yosys -p "read_verilog top.v; synth_gowin -json top-synth.json -family gw5a"
```
The old version of Yosys simply won't compile the design due to the lack
of port descriptions, while the new version will compile without errors.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
- consistently use value semantics for objects passed along FFI boundary
(not ideal but matches previous behavior)
- add new overload of RTLIL::Module: addMemory that does not require a "donor" object
- the idea is `Module`, `Memory`, `Wire`, `Cell` and `Process` cannot be directly constructed in Python and can only be added to the existing memory hierarchy in `Design` using the `add` methods - `Memory` requiring a donor object was the odd one out here
- fix superclass member wrapping only looking at direct superclass for inheritance instead of recursively checking superclasses
- fix superclass member wrapping not using superclass's denylists
- fix Design's `__str__` function not returning a string
- fix the generator crashing if there's any `std::function` in a header
- misc: add a crude `__repr__` based on `__str__`
Process the WRITE_MODE in the GW5A series in a more concise manner.
You can check it in the same way as in
https://github.com/YosysHQ/yosys/pull/5440
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
All supported (and planned to be supported) GW5A series chips do not
support the 2: Read-before-Write write mode.
Here, we prohibit the generation of BSRAM with this mode.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
