5077 commits

Author	SHA1	Message	Date
Emil J. Tywoniak	dacfded6d5	memory_map: propagate Mem src onto every generated cell	2026-07-17 23:49:06 +02:00
Emil J. Tywoniak	9cebc6e412	patch: split into single-output patch + multi-output patch_ports; drop input-cone gc	2026-07-17 23:49:06 +02:00
Emil J. Tywoniak	f977f3e9ad	patch: merge src into existing cells; opt_merge/_inc + onehot + ff.cc use Patch	2026-07-17 23:49:06 +02:00
Emil J. Tywoniak	19b6338e52	utils: add BitGrouper for shared bit-partition logic	2026-07-17 23:49:06 +02:00
Emil J. Tywoniak	738b46941a	opt_expr: convert remaining rewrites to patcher	2026-07-17 23:49:06 +02:00
Emil J. Tywoniak	d8b07abe54	opt_expr: evener morer patcherer	2026-07-17 23:48:59 +02:00
Emil J. Tywoniak	c4e3d0a955	opt_expr: even more patcher	2026-07-17 23:48:59 +02:00
Emil J. Tywoniak	20a3d95fea	opt_expr: more patcher again	2026-07-17 23:48:59 +02:00
Emil J. Tywoniak	fd67ce2b80	WIP	2026-07-17 23:48:54 +02:00
Emil J. Tywoniak	7652b1b52e	opt_expr: WIP use patcher more	2026-07-17 23:48:18 +02:00
Emil J. Tywoniak	1cedea0e60	opt_expr: cleanup	2026-07-17 23:48:12 +02:00
Emil J. Tywoniak	93a34b3d8b	opt_expr: cleanup	2026-07-17 23:48:12 +02:00
Emil J. Tywoniak	c7467e7edd	patch: infer leaves for gc	2026-07-17 23:48:12 +02:00
Emil J. Tywoniak	19d007cd65	patch: instead of cell->cell, use port->sig rewrites	2026-07-17 23:48:12 +02:00
Emil J. Tywoniak	f12f99afa6	opt_expr: use patcher for xor constant folding	2026-07-17 23:48:12 +02:00
Emil J. Tywoniak	07d5115135	patch: source transfer	2026-07-17 23:48:06 +02:00
Emil J. Tywoniak	71f7f586aa	patch: working multi-cell signorm invariant	2026-07-17 23:48:06 +02:00
Emil J. Tywoniak	2c1d114cb1	patch: WIP multicell patch test	2026-07-17 23:48:00 +02:00
Emil J. Tywoniak	9f0c1843d3	patch: signorm, move	2026-07-17 23:48:00 +02:00
Emil J. Tywoniak	a00631595f	patch: unique heap	2026-07-17 23:48:00 +02:00
Emil J. Tywoniak	240dda9186	test_patch total basics	2026-07-17 23:47:35 +02:00
Emil J. Tywoniak	628cb4f4ca	check: check bufnorm too	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	9153c11b56	check: check signorm indices and wires	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	c9fb05efd6	opt_merge: newcelltypes	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	6336c0a602	opt_merge: factor out hashing code across incremental and parallel	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	a582aceaca	opt_expr: replace invert_map with signorm traversal	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	061cec3166	check: fix memory bug in $connect	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	25e7118e4a	memory_bram: create blackboxes	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	76d8b2c2ea	Revert "memory: add -bram-register" ... This reverts commit 2bc6ea7f37f5c239491e83a3a8672af8954550ab.	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	6f09e55c95	Revert "memory_bram: add -register" ... This reverts commit b4b5093a14e5dceded852c644e70bf6ff447bba3.	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	c8208db681	flatten: disable signorm	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	2291084045	pmgen: hold sigmap pointer instead of owning it	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	92475ecf62	equiv_miter: don't copy $input_port	2026-07-17 23:33:03 +02:00
Emil J. Tywoniak	15bd3bcfad	design: properly switch signorm mode when restoring saved designs	2026-07-17 23:33:03 +02:00
Emil J. Tywoniak	52ae92380d	equiv_make: don't copy $input_port	2026-07-17 23:33:03 +02:00
Emil J. Tywoniak	b0e9dab15a	Revert "techmap: call hierarchy on map files to determine port directions" ... This reverts commit eabbf6d22527f386811c7b507f74f887a258b397.	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	6ca6d4281f	hierarchy: tolerance for apparent recursive instances in techmap files	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	e82e1aeaad	techmap: call hierarchy on map files to determine port directions	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	eecab792a3	memory: add -bram-register	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	5b836f1b2b	memory_bram: add -register	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	de7f38087d	opt_expr: with -keepdc disable equality optimization rules that break when ports are sigmapped	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	79386f652f	connect: remove input ports on conflict	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	f4d180e78f	opt_dff: sigma harder, FfDataSigMapped	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	df94483b9f	opt_dff: temporarily disable signorm due to muxtree traversal	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	f06d67a031	design: fix signorm commit connectivity to design	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	728fe21917	flatten: redo signormalization to work around fanout issue	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	b3baa75528	signorm: disable passes that use rewrite_sigspecs	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	7528cb3157	check: stitch info about $connect ports together for driver analysis	2026-07-17 23:32:53 +02:00
Emil J. Tywoniak	23e37193b4	abstract: skip $input_port cells	2026-07-17 23:32:34 +02:00
Emil J. Tywoniak	1350c0da92	flatten: skip $input_port cells in template module	2026-07-17 23:32:34 +02:00