1630 commits

Author	SHA1	Message	Date
Eddie Hung	a56d6970f2	Revert "Merge pull request #1598 from YosysHQ/revert-1588-eddie/xaiger_cleanup" ... This reverts commit 92654f73ea, reversing changes made to 3e14ff1667.	2019-12-27 16:05:58 -08:00
Eddie Hung	9e6632c40a	Merge branch 'master' of github.com:YosysHQ/yosys	2019-12-27 15:37:26 -08:00
Eddie Hung	3d4644804e	write_xaiger: simplify c{i,o}_bits	2019-12-27 15:37:17 -08:00
David Shah	df31ade3b3	Revert "write_xaiger: only instantiate each whitebox cell type once"	2019-12-27 23:25:20 +00:00
Eddie Hung	dd503a5f3f	Really fix it!	2019-12-27 15:18:55 -08:00
Eddie Hung	49881b4468	write_xaiger: fix arrival times for non boxes	2019-12-27 11:30:18 -08:00
Eddie Hung	6eadd4390a	write_xaiger to opt instead of just clean whiteboxes	2019-12-23 08:35:53 -08:00
Eddie Hung	a75e08c709	write_xaiger: only instantiate each whitebox cell type once	2019-12-20 13:07:24 -08:00
Eddie Hung	10e82e103f	Revert "Optimise write_xaiger"	2019-12-20 12:05:45 -08:00
Eddie Hung	5f50e4f112	Cleanup xaiger, remove unnecessary complexity with inout	2019-12-17 15:45:26 -08:00
Eddie Hung	e82a9bc642	Do not sigmap	2019-12-17 00:03:03 -08:00
Eddie Hung	2e71130700	Revert "Use sigmap signal" ... This reverts commit 42f990f3a6.	2019-12-17 00:00:07 -08:00
Eddie Hung	42f990f3a6	Use sigmap signal	2019-12-16 16:49:42 -08:00
Eddie Hung	b19fc8839b	Skip $inout transformation if not a PI	2019-12-16 14:39:13 -08:00
Eddie Hung	78c0246d4a	Revert "write_xaiger: use sigmap bits more consistently" ... This reverts commit 6c340112fe.	2019-12-16 14:35:35 -08:00
Eddie Hung	6c340112fe	write_xaiger: use sigmap bits more consistently	2019-12-16 10:21:57 -08:00
Eddie Hung	91467938c4	Stray newline	2019-12-06 17:08:19 -08:00
Eddie Hung	f2ac36de4a	write_xaiger to inst each cell type once, do not call techmap/aigmap	2019-12-06 17:06:10 -08:00
Eddie Hung	1f96de04c9	Fix writing non-whole modules, including inouts and keeps	2019-12-06 16:19:10 -08:00
Eddie Hung	a682a3cf93	write_xaiger to support part-selected modules again	2019-12-05 17:54:43 -08:00
Eddie Hung	c6ee2fb482	Cleanup	2019-12-03 19:21:47 -08:00
Eddie Hung	df52bc80d8	write_xaiger to consume abc9_init attribute for abc9_flops	2019-12-03 18:47:44 -08:00
Eddie Hung	419ca5c207	Revert "Fold loop" ... This reverts commit a30d5e1cc3.	2019-11-27 21:55:56 -08:00
Eddie Hung	449b1d2c6f	Add comment, use sigmap	2019-11-27 13:20:12 -08:00
Eddie Hung	403214f44d	Revert "Fold loop" ... This reverts commit da51492dbc.	2019-11-27 12:35:25 -08:00
Eddie Hung	5e67df38ed	latch -> box	2019-11-26 22:59:05 -08:00
Eddie Hung	a30d5e1cc3	Fold loop	2019-11-26 21:57:50 -08:00
Eddie Hung	68717dd03b	Do not sigmap keep bits inside write_xaiger	2019-11-26 21:57:50 -08:00
Eddie Hung	7136cee6b4	xaiger: do not promote output wires	2019-11-26 21:55:37 -08:00
Eddie Hung	99702efaba	xaiger: do not promote output wires	2019-11-26 19:03:02 -08:00
Eddie Hung	da51492dbc	Fold loop	2019-11-25 15:43:37 -08:00
Eddie Hung	7f0914a408	Do not sigmap keep bits inside write_xaiger	2019-11-25 15:42:07 -08:00
Eddie Hung	81548d1ef9	write_xaiger back to working with whole modules only	2019-11-22 16:52:17 -08:00
Eddie Hung	8ef241c6f4	Revert "write_xaiger to not use module POs but only write outputs if driven" ... This reverts commit 0ab1e496dc.	2019-11-22 13:24:28 -08:00
Eddie Hung	0ab1e496dc	write_xaiger to not use module POs but only write outputs if driven	2019-11-21 16:19:28 -08:00
Eddie Hung	929beda19c	abc9 to support async flops $_DFF_[NP][NP][01]_	2019-11-19 16:57:26 -08:00
Eddie Hung	09ee96e8c2	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-11-19 15:40:39 -08:00
whitequark	3c643c57df	write_verilog: add -extmem option, to write split memory init files. ... Some toolchains (in particular Quartus) are pathologically slow if a large amount of assignments in `initial` blocks are used.	2019-11-18 01:27:21 +00:00
Clifford Wolf	cd44826d50	Use cell name for btor bad state props when it is a public name ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-11-14 11:57:38 +01:00
Makai Mann	d88cc139a0	Add an info string symbol for bad states in btor backend	2019-11-11 16:40:51 -08:00
Clifford Wolf	5110a34dd7	Fix write_aiger bug added in 524af21 ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-11-04 14:25:13 +01:00
Clifford Wolf	81876a3734	Merge pull request #1393 from whitequark/write_verilog-avoid-init ... write_verilog: do not print (*init*) attributes on regs	2019-10-27 10:25:01 +01:00
Clifford Wolf	f02623abb5	Bugfix in smtio vcd handling of $-identifiers ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-10-23 00:04:34 +02:00
Eddie Hung	b2e34f932a	Rename $currQ to $abc9_currQ	2019-10-07 15:31:43 -07:00
Eddie Hung	90a954bb9c	Get rid of latch_* in write_xaiger	2019-10-07 13:09:13 -07:00
Eddie Hung	1504ca2cd9	Remove "write_xaiger -zinit"	2019-10-07 11:58:49 -07:00
Eddie Hung	e1554b56dd	Add comment on default flop init	2019-10-07 11:56:17 -07:00
Eddie Hung	d9fba95177	Get rid of output_port lookup	2019-10-07 11:49:06 -07:00
Eddie Hung	3879ca1398	Do not require changes to cells_sim.v; try and work out comb model	2019-10-05 22:55:18 -07:00
Eddie Hung	3c6e5d82a6	Error if $currQ not found	2019-10-05 09:06:13 -07:00