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https://github.com/YosysHQ/yosys
synced 2025-10-31 11:42:30 +00:00
Fix writing non-whole modules, including inouts and keeps
This commit is contained in:
Eddie Hung
parent
ec0acc9f85
commit
1f96de04c9
1 changed files with 81 additions and 90 deletions
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@ -142,7 +142,7 @@ struct XAigerWriter
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{
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pool<SigBit> undriven_bits;
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pool<SigBit> unused_bits;
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pool<SigBit> keep_bits;
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pool<SigBit> inout_bits;
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// promote public wires
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for (auto wire : module->wires())
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@ -154,60 +154,45 @@ struct XAigerWriter
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if (wire->port_input)
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sigmap.add(wire);
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// promote output wires
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// promote keep wires
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for (auto wire : module->wires())
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if (wire->port_output)
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if (wire->get_bool_attribute(ID::keep))
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sigmap.add(wire);
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for (auto wire : module->wires())
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{
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bool keep = wire->attributes.count("\\keep");
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for (int i = 0; i < GetSize(wire); i++)
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{
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SigBit wirebit(wire, i);
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SigBit bit = sigmap(wirebit);
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if (bit.wire) {
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undriven_bits.insert(bit);
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unused_bits.insert(bit);
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}
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if (keep) {
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keep_bits.insert(wirebit);
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if (bit != wirebit)
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alias_map[wirebit] = bit;
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input_bits.insert(wirebit);
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output_bits.insert(wirebit);
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if (bit.wire == nullptr) {
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if (wire->port_output) {
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aig_map[wirebit] = (bit == State::S1) ? 1 : 0;
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if (holes_mode)
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output_bits.insert(wirebit);
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//external_bits.insert(wirebit);
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}
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continue;
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}
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if (wire->port_input) {
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if (bit != wirebit)
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alias_map[bit] = wirebit;
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input_bits.insert(wirebit);
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}
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undriven_bits.insert(bit);
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unused_bits.insert(bit);
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if (wire->port_input)
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input_bits.insert(bit);
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if (wire->port_output) {
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if (bit != RTLIL::Sx) {
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if (bit != wirebit)
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alias_map[wirebit] = bit;
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if (holes_mode)
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output_bits.insert(wirebit);
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else
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external_bits.insert(wirebit);
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}
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if (bit != wirebit)
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alias_map[wirebit] = bit;
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if (holes_mode)
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output_bits.insert(wirebit);
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else
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log_debug("Skipping PO '%s' driven by 1'bx\n", log_signal(wirebit));
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external_bits.insert(wirebit);
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}
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}
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}
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// Cannot fold into above due to use of sigmap
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for (auto bit : input_bits)
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undriven_bits.erase(sigmap(bit));
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for (auto bit : output_bits)
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unused_bits.erase(sigmap(bit));
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if (wire->port_input && wire->port_output)
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inout_bits.insert(bit);
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}
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// TODO: Speed up toposort -- ultimately we care about
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// box ordering, but not individual AIG cells
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@ -307,10 +292,9 @@ struct XAigerWriter
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if (I != b)
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alias_map[b] = I;
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output_bits.insert(b);
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unused_bits.erase(I);
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if (!cell_known)
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keep_bits.insert(b);
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inout_bits.insert(b);
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}
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}
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}
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@ -328,11 +312,10 @@ struct XAigerWriter
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for (auto b : c.second) {
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Wire *w = b.wire;
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if (!w) continue;
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input_bits.insert(b);
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SigBit O = sigmap(b);
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if (O != b)
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alias_map[O] = b;
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undriven_bits.erase(O);
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input_bits.insert(b);
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if (arrival)
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arrival_times[b] = arrival;
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@ -343,12 +326,6 @@ struct XAigerWriter
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//log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
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}
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for (auto cell : module->cells())
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if (!module->selected(cell))
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for (auto &conn : cell->connections())
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for (auto bit : sigmap(conn.second))
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external_bits.insert(bit);
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if (abc9_box_seen) {
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dict<IdString, std::pair<IdString,int>> flop_q;
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for (auto cell : flop_boxes) {
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@ -494,8 +471,8 @@ struct XAigerWriter
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SigBit O = sigmap(b);
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if (O != b)
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alias_map[O] = b;
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undriven_bits.erase(O);
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input_bits.erase(b);
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undriven_bits.erase(O);
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}
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}
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}
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@ -528,56 +505,70 @@ struct XAigerWriter
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// TODO: Free memory from toposort, bit_drivers, bit_users
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}
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for (auto bit : input_bits) {
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if (!output_bits.count(bit))
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if (!holes_mode)
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for (auto cell : module->cells())
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if (!module->selected(cell))
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for (auto &conn : cell->connections())
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if (cell->input(conn.first))
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for (auto wirebit : conn.second)
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if (sigmap(wirebit).wire)
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external_bits.insert(wirebit);
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// For all bits consumed outside of the selected cells,
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// but driven from a selected cell, then add it as
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// a primary output
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for (auto wirebit : external_bits) {
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SigBit bit = sigmap(wirebit);
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if (!bit.wire)
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continue;
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RTLIL::Wire *wire = bit.wire;
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// If encountering an inout port, or a keep-ed wire, then create a new wire
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// with $inout.out suffix, make it a PO driven by the existing inout, and
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// inherit existing inout's drivers
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if ((wire->port_input && wire->port_output && !undriven_bits.count(bit))
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|| keep_bits.count(bit)) {
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RTLIL::IdString wire_name = stringf("$%s$inout.out", wire->name.c_str());
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RTLIL::Wire *new_wire = module->wire(wire_name);
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if (!new_wire)
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new_wire = module->addWire(wire_name, GetSize(wire));
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SigBit new_bit(new_wire, bit.offset);
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module->connect(new_bit, bit);
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if (not_map.count(bit)) {
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auto a = not_map.at(bit);
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not_map[new_bit] = a;
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}
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else if (and_map.count(bit)) {
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auto a = and_map.at(bit);
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and_map[new_bit] = a;
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}
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else if (alias_map.count(bit)) {
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auto a = alias_map.at(bit);
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alias_map[new_bit] = a;
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}
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else
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alias_map[new_bit] = bit;
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output_bits.erase(bit);
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output_bits.insert(new_bit);
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if (!undriven_bits.count(bit)) {
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if (bit != wirebit)
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alias_map[wirebit] = bit;
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output_bits.insert(wirebit);
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}
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}
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for (auto bit : external_bits)
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if (!undriven_bits.count(sigmap(bit))) {
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output_bits.insert(bit);
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unused_bits.erase(sigmap(bit));
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}
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for (auto bit : input_bits)
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undriven_bits.erase(sigmap(bit));
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for (auto bit : output_bits)
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unused_bits.erase(sigmap(bit));
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for (auto bit : unused_bits)
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undriven_bits.erase(bit);
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if (!undriven_bits.empty() && !holes_mode) {
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//undriven_bits.sort();
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// Make all undriven bits a primary input
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if (!holes_mode)
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for (auto bit : undriven_bits) {
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//log_warning("Treating undriven bit %s.%s like $anyseq.\n", log_id(module), log_signal(bit));
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input_bits.insert(bit);
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undriven_bits.erase(bit);
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}
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//log_warning("Treating a total of %d undriven bits in %s like $anyseq.\n", GetSize(undriven_bits), log_id(module));
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// For inout ports, or keep-ed wires, then create a new wire with an
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// $inout.out suffix, make it a PO driven by the existing inout, and
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// inherit existing inout's drivers
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for (auto bit : inout_bits) {
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RTLIL::Wire *wire = bit.wire;
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RTLIL::IdString wire_name = stringf("$%s$inout.out", wire->name.c_str());
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RTLIL::Wire *new_wire = module->wire(wire_name);
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if (!new_wire)
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new_wire = module->addWire(wire_name, GetSize(wire));
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SigBit new_bit(new_wire, bit.offset);
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module->connect(new_bit, bit);
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if (not_map.count(bit)) {
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auto a = not_map.at(bit);
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not_map[new_bit] = a;
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}
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else if (and_map.count(bit)) {
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auto a = and_map.at(bit);
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and_map[new_bit] = a;
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}
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else if (alias_map.count(bit)) {
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auto a = alias_map.at(bit);
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alias_map[new_bit] = a;
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}
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else
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alias_map[new_bit] = bit;
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output_bits.erase(bit);
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output_bits.insert(new_bit);
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}
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if (holes_mode) {
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@ -880,7 +871,7 @@ struct XAigerWriter
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for (auto it = holes_module->cells_.begin(); it != holes_module->cells_.end(); ) {
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auto cell = it->second;
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if (cell->type.in("$_DFF_N_", "$_DFF_NN0_", "$_DFF_NN1_", "$_DFF_NP0_", "$_DFF_NP1_",
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"$_DFF_P_", "$_DFF_PN0_", "$_DFF_PN1", "$_DFF_PP0_", "$_DFF_PP1_")) {
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"$_DFF_P_", "$_DFF_PN0_", "$_DFF_PN1", "$_DFF_PP0_", "$_DFF_PP1_")) {
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SigBit D = cell->getPort("\\D");
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SigBit Q = cell->getPort("\\Q");
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// Remove the DFF cell from what needs to be a combinatorial box
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