700 commits

Author	SHA1	Message	Date
Florian Zeitz	0491042849	Check base-n literals only contain valid digits	2015-08-17 15:37:33 +02:00
Florian Zeitz	64ccbf8510	Warn on literals exceeding the specified bit width	2015-08-17 15:27:35 +02:00
Larry Doolittle	6c00704a5e	Another block of spelling fixes ... Smaller this time	2015-08-14 23:27:05 +02:00
Larry Doolittle	022f570563	Keep gcc from complaining about uninitialized variables	2015-08-14 23:26:49 +02:00
Clifford Wolf	0350074819	Re-created command-reference-manual.tex, copied some doc fixes to online help	2015-08-14 11:27:19 +02:00
Clifford Wolf	84bf862f7c	Spell check (by Larry Doolittle)	2015-08-14 10:56:05 +02:00
Clifford Wolf	e4ef000b70	Adjust makefiles to work with out-of-tree builds ... This is based on work done by Larry Doolittle	2015-08-12 15:04:44 +02:00
Clifford Wolf	45ee2ba3b8	Fixed handling of [a-fxz?] in decimal constants	2015-08-11 11:32:37 +02:00
Marcus Comstedt	c836faae3e	Add -noautowire option to verilog frontend	2015-08-01 12:16:54 +02:00
Clifford Wolf	8d6d5c30d9	Added WORDS parameter to $meminit	2015-07-31 10:40:09 +02:00
Clifford Wolf	4513ff1b85	Fixed nested mem2reg	2015-07-29 16:37:08 +02:00
Clifford Wolf	6c84341f22	Fixed trailing whitespaces	2015-07-02 11:14:30 +02:00
Clifford Wolf	13983e8318	Fixed handling of parameters with reversed range	2015-06-08 14:03:06 +02:00
Clifford Wolf	99b8746d27	Fixed signedness of genvar expressions	2015-05-29 20:08:00 +02:00
Clifford Wolf	08a4af3cde	Improvements in BLIF front-end	2015-05-24 08:03:21 +02:00
Clifford Wolf	6061b7bd58	bugfix in blif front-end	2015-05-18 11:15:49 +02:00
Clifford Wolf	3ecb2bf067	Improved .latch support in BLIF front-end	2015-05-17 18:58:24 +02:00
Clifford Wolf	2cc4e75914	Added read_blif command	2015-05-17 15:25:03 +02:00
Clifford Wolf	e5116eeb77	Generalized blifparse API	2015-05-17 15:10:37 +02:00
Clifford Wolf	7dad017c9c	abc/blifparse files reorganization	2015-05-17 14:44:28 +02:00
Clifford Wolf	61512b6f41	Verific build fixes	2015-05-17 08:19:52 +02:00
Clifford Wolf	7ff802e199	Verilog front-end: define `BLACKBOX in -lib mode	2015-04-19 21:30:46 +02:00
Clifford Wolf	a923a63a89	Ignore celldefine directive in verilog front-end	2015-03-25 19:46:12 +01:00
Clifford Wolf	422794c584	Const-fold parameter defs on-demand in AstNode::detectSignWidthWorker()	2015-03-01 11:20:22 +01:00
Clifford Wolf	1f1deda888	Added non-std verilog assume() statement	2015-02-26 18:47:39 +01:00
Clifford Wolf	d5ce9a32ef	Added deep recursion warning to AST simplify	2015-02-20 10:33:20 +01:00
Clifford Wolf	dc1a0f06fc	Parser support for complex delay expressions	2015-02-20 10:21:36 +01:00
Clifford Wolf	e0e6d130cd	YosysJS stuff	2015-02-19 13:36:54 +01:00
Clifford Wolf	c2ba4fb2fd	Convert floating point cell parameters to strings	2015-02-18 23:35:23 +01:00
Clifford Wolf	e9368a1d7e	Various fixes for memories with offsets	2015-02-14 14:21:15 +01:00
Clifford Wolf	7f1a1759d7	Added "read_verilog -nomeminit" and "nomeminit" attribute	2015-02-14 11:21:12 +01:00
Clifford Wolf	a8e9d37c14	Creating $meminit cells in verilog front-end	2015-02-14 10:49:30 +01:00
Clifford Wolf	ef151b0b30	Fixed handling of "//" in filenames in verilog pre-processor	2015-02-14 08:41:03 +01:00
Clifford Wolf	cd919abdf1	Added AstNode::simplify() recursion counter	2015-02-13 12:33:12 +01:00
Clifford Wolf	4f68a77e3f	Improved read_verilog support for empty behavioral statements	2015-02-10 12:17:29 +01:00
Clifford Wolf	234a45a3d5	Ignore explicit assignments to constants in HDL code	2015-02-08 00:58:03 +01:00
Clifford Wolf	c8305e3a6d	Fixed a bug with autowire bit size ... (removed leftover from when we tried to auto-size the wires)	2015-02-08 00:48:23 +01:00
Clifford Wolf	2a9ad48eb6	Added ENABLE_NDEBUG makefile options	2015-01-24 12:16:46 +01:00
Clifford Wolf	df9d096a7d	Ignoring more system task and functions	2015-01-15 13:08:19 +01:00
Clifford Wolf	a588a4a5c9	Fixed handling of "input foo; reg [0:0] foo;"	2015-01-15 12:53:12 +01:00
Clifford Wolf	8e8e791fb5	Consolidate "Blocking assignment to memory.." msgs for the same line	2015-01-15 12:41:52 +01:00
Fabio Utzig	fff6f00b3c	Enable bison to be customized	2015-01-08 09:56:20 -02:00
Clifford Wolf	1bd67d792e	Define YOSYS and SYNTHESIS in preproc	2015-01-02 17:11:54 +01:00
Clifford Wolf	eefe78be09	Fixed memory->start_offset handling	2015-01-01 12:56:01 +01:00
Clifford Wolf	0bb6b24c11	Added global yosys_celltypes	2014-12-29 14:30:33 +01:00
Clifford Wolf	90bc71dd90	dict/pool changes in ast	2014-12-29 03:11:50 +01:00
Clifford Wolf	137f35373f	Changed more code to dict<> and pool<>	2014-12-28 19:24:24 +01:00
Clifford Wolf	7751c491fb	Improved some warning messages	2014-12-27 03:40:27 +01:00
Clifford Wolf	12ca6538a4	Fixed mem2reg warning message	2014-12-27 03:26:30 +01:00
Clifford Wolf	a6c96b986b	Added Yosys::{dict,nodict,vector} container types	2014-12-26 10:53:21 +01:00