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Ignore celldefine directive in verilog front-end

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Clifford Wolf 2015-03-25 19:46:12 +01:00
parent e468d4cc60
commit a923a63a89
1 changed files with 3 additions and 0 deletions
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frontends/verilog/verilog_lexer.l
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@ -116,6 +116,9 @@ YOSYS_NAMESPACE_END
"`timescale"[ \t]+[^ \t\r\n/]+[ \t]*"/"[ \t]*[^ \t\r\n]* /* ignore timescale directive */
"`celldefine"[^\n]* /* ignore `celldefine */
"`endcelldefine"[^\n]* /* ignore `endcelldefine */
"`default_nettype"[ \t]+[^ \t\r\n/]+ {
char *p = yytext;
while (*p != 0 && *p != ' ' && *p != '\t') p++;