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Re-created command-reference-manual.tex, copied some doc fixes to online help
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10 changed files with 668 additions and 52 deletions
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@ -40,14 +40,14 @@ static std::vector<std::string> verilog_defaults;
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static std::list<std::vector<std::string>> verilog_defaults_stack;
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struct VerilogFrontend : public Frontend {
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VerilogFrontend() : Frontend("verilog", "read modules from verilog file") { }
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VerilogFrontend() : Frontend("verilog", "read modules from Verilog file") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" read_verilog [options] [filename]\n");
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log("\n");
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log("Load modules from a verilog file to the current design. A large subset of\n");
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log("Load modules from a Verilog file to the current design. A large subset of\n");
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log("Verilog-2005 is supported.\n");
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log("\n");
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log(" -sv\n");
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@ -65,7 +65,7 @@ struct VerilogFrontend : public Frontend {
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log(" dump abstract syntax tree (after simplification)\n");
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log("\n");
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log(" -dump_vlog\n");
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log(" dump ast as verilog code (after simplification)\n");
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log(" dump ast as Verilog code (after simplification)\n");
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log("\n");
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log(" -yydebug\n");
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log(" enable parser debug output\n");
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@ -102,7 +102,7 @@ struct VerilogFrontend : public Frontend {
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log(" memories to registers directly in the front-end.\n");
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log("\n");
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log(" -ppdump\n");
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log(" dump verilog code after pre-processor\n");
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log(" dump Verilog code after pre-processor\n");
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log("\n");
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log(" -nopp\n");
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log(" do not run the pre-processor\n");
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@ -145,7 +145,7 @@ struct VerilogFrontend : public Frontend {
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log("\n");
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log("Note that the Verilog frontend does a pretty good job of processing valid\n");
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log("verilog input, but has not very good error reporting. It generally is\n");
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log("recommended to use a simulator (for example icarus verilog) for checking\n");
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log("recommended to use a simulator (for example Icarus Verilog) for checking\n");
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log("the syntax of the code, rather than to rely on read_verilog for that.\n");
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log("\n");
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}
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@ -345,7 +345,7 @@ struct VerilogDefaults : public Pass {
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log("\n");
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log(" verilog_defaults -clear");
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log("\n");
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log("Clear the list of verilog default options.\n");
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log("Clear the list of Verilog default options.\n");
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log("\n");
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log("\n");
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log(" verilog_defaults -push");
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