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Author SHA1 Message Date
Eddie Hung
979bf36fb0 Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_t 2019-12-19 11:23:41 -08:00
Eddie Hung
94f15f023c Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-19 10:29:40 -08:00
Eddie Hung
269ba56a6d
Merge pull request #1581 from YosysHQ/clifford/fix1565 
Fix sim for assignments with lhs<rhs size
 2019-12-19 12:24:27 -05:00
Eddie Hung
df626ee7ab
Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanup 
Optimise write_xaiger
 2019-12-19 12:24:03 -05:00
Eddie Hung
d406f2ffd7
Merge pull request #1569 from YosysHQ/eddie/fix_1531 
verilog: preserve size of $genval$-s in for loops
 2019-12-19 12:21:33 -05:00
Eddie Hung
d675f22f4e
Merge pull request #1571 from YosysHQ/eddie/fix_1570 
mem_arst.v: do not redeclare ANSI port
 2019-12-19 12:21:22 -05:00
Marcin Kościelnicki
8b2c9f4518 xilinx: Add simulation models for remaining CLB primitives. 2019-12-19 18:04:04 +01:00
Marcin Kościelnicki
561ae1c5c4 xilinx_dffopt: Keep order of LUT inputs. 
See rationale at https://github.com/YosysHQ/yosys/pull/1557#discussion_r359196549
 2019-12-19 18:01:43 +01:00
Eddie Hung
76ba06a79e Bump ABC again 2019-12-18 15:14:38 -08:00
Eddie Hung
3b559de6e9 Interpret "abc9 -lut" as lut string only if [0-9:] 2019-12-18 12:21:12 -08:00
Eddie Hung
f52c6efd9d Add "scratchpad" to CHANGELOG 2019-12-18 12:09:11 -08:00
Eddie Hung
d0afe4e10d Merge branch 'master' of github.com:YosysHQ/yosys 2019-12-18 12:08:38 -08:00
David Shah
520f1646cf
Merge pull request #1563 from YosysHQ/dave/async-prld 
ecp5: Add support for mapping PRLD FFs
 2019-12-18 19:42:17 +00:00
Eddie Hung
b2a42e1fac
Merge pull request #1572 from nakengelhardt/scratchpad_pass 
add a command to read/modify scratchpad contents
 2019-12-18 13:55:44 -05:00
Eddie Hung
dd71ac5cc9
Merge pull request #1584 from YosysHQ/mwk/xilinx-flaky-test 
tests/xilinx: fix flaky mux test
 2019-12-18 12:53:45 -05:00
Marcin Kościelnicki
f382164d6e tests/xilinx: fix flaky mux test 2019-12-18 15:53:29 +01:00
Marcin Kościelnicki
a235250403 xilinx: Add xilinx_dffopt pass (#1557) 2019-12-18 13:43:43 +01:00
Marcin Kościelnicki
aff6ad1ce0 xilinx: Improve flip-flop handling. 
This adds support for infering more kinds of flip-flops:

- FFs with async set/reset and clock enable
- FFs with sync set/reset
- FFs with sync set/reset and clock enable

Some passes have been moved (and some added) in order for dff2dffs to
work correctly.

This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop
capabilities (though not latch capabilities).  Older FPGAs also support
having both a set and a reset input, which will be handled at a later
data.
 2019-12-18 13:43:43 +01:00
Clifford Wolf
22dd9f107c Send people to symbioticeda.com instead of verific.com 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-12-18 13:06:34 +01:00
N. Engelhardt
3671ecc7d0 use extra_args 2019-12-18 12:30:30 +01:00
Eddie Hung
c9c77a90b3 Remove &verify -s 2019-12-17 16:11:54 -08:00
Eddie Hung
5e206199f4 Bump ABC for upstream fix 2019-12-17 16:11:37 -08:00
Eddie Hung
b1b99e421e Use pool<> instead of std::set<> to preserver ordering 2019-12-17 16:10:40 -08:00
Eddie Hung
a6fdb9f5c1 aiger frontend to user shorter, $-prefixed, names 2019-12-17 15:50:01 -08:00
Eddie Hung
5f50e4f112 Cleanup xaiger, remove unnecessary complexity with inout 2019-12-17 15:45:26 -08:00
Eddie Hung
0875a07871 read_xaiger to cope with optional '\n' after 'c' 2019-12-17 15:45:26 -08:00
N. Engelhardt
c8bc1793a4 check scratchpad variable abc9.scriptfile 2019-12-17 19:39:55 +01:00
Clifford Wolf
41ed6ca7a5 Fix sim for assignments with lhs<rhs size, fixes #1565 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-12-17 17:36:30 +01:00
Eddie Hung
dccd7eb39f Cleanup 2019-12-17 00:25:08 -08:00
Eddie Hung
e82a9bc642 Do not sigmap 2019-12-17 00:03:03 -08:00
Eddie Hung
2e71130700 Revert "Use sigmap signal" 
This reverts commit 42f990f3a6.
 2019-12-17 00:00:07 -08:00
Eddie Hung
a73f96594f
Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram 
xilinx: add LUTRAM rules for RAM32M, RAM64M
 2019-12-16 21:48:21 -08:00
Eddie Hung
9935370ada
Merge pull request #1521 from dh73/diego/memattr 
Adding support for Xilinx memory attribute 'block' in single port mode.
 2019-12-16 21:48:02 -08:00
Eddie Hung
aed67dd020 abc9 needs a clean afterwards 2019-12-16 18:42:23 -08:00
Eddie Hung
33e6d05585 Enforce non-existence 2019-12-16 17:06:30 -08:00
Eddie Hung
d9bf7061cd Put $__ABC9_{FF_,ASYNC} into same clock domain as abc9_flop 2019-12-16 16:49:48 -08:00
Eddie Hung
42f990f3a6 Use sigmap signal 2019-12-16 16:49:42 -08:00
Eddie Hung
187e1c46e6 Update doc 2019-12-16 14:48:53 -08:00
Eddie Hung
b19fc8839b Skip $inout transformation if not a PI 2019-12-16 14:39:13 -08:00
Eddie Hung
78c0246d4a Revert "write_xaiger: use sigmap bits more consistently" 
This reverts commit 6c340112fe.
 2019-12-16 14:35:35 -08:00
Eddie Hung
378d9e6e0c Add another test 2019-12-16 13:57:55 -08:00
Eddie Hung
4158ce4eda More sloppiness, thanks @dh73 for spotting 2019-12-16 13:56:45 -08:00
Eddie Hung
db0003410f Accidentally commented out tests 2019-12-16 13:31:47 -08:00
Eddie Hung
5a00d5578c Add unconditional match blocks for force RAM 2019-12-16 13:31:15 -08:00
Eddie Hung
6b384861e4 Oops 2019-12-16 13:31:05 -08:00
Eddie Hung
e990c013c5 Merge blockram tests 2019-12-16 13:01:51 -08:00
Eddie Hung
d910bec8e0 Update xc7/xcu bram rules 2019-12-16 13:00:58 -08:00
Eddie Hung
503d1db551 Implement 'attributes' grammar 2019-12-16 12:58:13 -08:00
Eddie Hung
952d62991f Merge branch 'diego/memattr' of https://github.com/dh73/yosys into diego/memattr 2019-12-16 12:07:49 -08:00
Eddie Hung
5d00996426 Merge branch 'eddie/xilinx_lutram' of github.com:YosysHQ/yosys into eddie/xilinx_lutram 2019-12-16 12:06:47 -08:00