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Merge pull request #1521 from dh73/diego/memattr
Adding support for Xilinx memory attribute 'block' in single port mode.
This commit is contained in:
commit
9935370ada
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@ -134,6 +134,7 @@ struct rules_t
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dict<string, int> min_limits, max_limits;
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bool or_next_if_better, make_transp, make_outreg;
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char shuffle_enable;
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vector<vector<std::tuple<bool,IdString,Const>>> attributes;
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};
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dict<IdString, vector<bram_t>> brams;
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@ -327,6 +328,20 @@ struct rules_t
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continue;
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}
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if (GetSize(tokens) >= 2 && tokens[0] == "attribute") {
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data.attributes.emplace_back();
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for (int idx = 1; idx <= GetSize(tokens)-1; idx++) {
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size_t c1 = tokens[idx][0] == '!' ? 1 : 0;
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size_t c2 = tokens[idx].find("=");
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bool exists = (c1 == 0);
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IdString key = RTLIL::escape_id(tokens[idx].substr(c1, c2));
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Const val = c2 != std::string::npos ? tokens[idx].substr(c2+1) : RTLIL::Const(1);
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data.attributes.back().emplace_back(exists, key, val);
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}
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continue;
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}
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syntax_error();
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}
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}
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@ -724,7 +739,7 @@ grow_read_ports:;
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if (match.make_transp && wr_ports <= 1) {
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pi.make_transp = true;
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if (pi.clocks != 0) {
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if (wr_ports == 1 && wr_clkdom != clkdom) {
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if (wr_ports == 1 && wr_clkdom != clkdom) {
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log(" Bram port %c%d.%d cannot have soft transparency logic added as read and write clock domains differ.\n", pi.group + 'A', pi.index + 1, pi.dupidx + 1);
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goto skip_bram_rport;
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}
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@ -813,6 +828,45 @@ grow_read_ports:;
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return false;
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}
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for (const auto &sums : match.attributes) {
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bool found = false;
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for (const auto &term : sums) {
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bool exists = std::get<0>(term);
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IdString key = std::get<1>(term);
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const Const &value = std::get<2>(term);
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auto it = cell->attributes.find(key);
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if (it == cell->attributes.end()) {
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if (exists)
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continue;
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found = true;
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break;
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}
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else if (!exists)
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continue;
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if (it->second != value)
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continue;
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found = true;
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break;
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}
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if (!found) {
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std::stringstream ss;
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bool exists = std::get<0>(sums.front());
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if (!exists)
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ss << "!";
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IdString key = std::get<1>(sums.front());
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ss << key.str();
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const Const &value = std::get<2>(sums.front());
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if (exists)
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ss << "=";
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if (value != Const(1))
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ss << "\"" << value.decode_string() << "\"";
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log(" Rule for bram type %s rejected: requirement 'attribute %s ...' not met.\n",
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log_id(match.name), ss.str().c_str());
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return false;
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}
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}
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if (mode == 1)
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return true;
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}
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@ -1100,6 +1154,45 @@ void handle_cell(Cell *cell, const rules_t &rules)
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goto next_match_rule;
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}
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for (const auto &sums : match.attributes) {
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bool found = false;
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for (const auto &term : sums) {
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bool exists = std::get<0>(term);
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IdString key = std::get<1>(term);
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const Const &value = std::get<2>(term);
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auto it = cell->attributes.find(key);
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if (it == cell->attributes.end()) {
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if (exists)
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continue;
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found = true;
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break;
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}
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else if (!exists)
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continue;
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if (it->second != value)
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continue;
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found = true;
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break;
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}
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if (!found) {
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std::stringstream ss;
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bool exists = std::get<0>(sums.front());
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if (!exists)
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ss << "!";
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IdString key = std::get<1>(sums.front());
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ss << key.str();
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const Const &value = std::get<2>(sums.front());
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if (exists)
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ss << "=";
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if (value != Const(1))
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ss << "\"" << value.decode_string() << "\"";
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log(" Rule for bram type %s (variant %d) rejected: requirement 'attribute %s ...' not met.\n",
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log_id(bram.name), bram.variant, ss.str().c_str());
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goto next_match_rule;
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}
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}
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log(" Rule #%d for bram type %s (variant %d) accepted.\n", i+1, log_id(bram.name), bram.variant);
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if (or_next_if_better || !best_rule_cache.empty())
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@ -1225,6 +1318,13 @@ struct MemoryBramPass : public Pass {
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log(" dcells ....... number of cells in 'data-direction'\n");
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log(" cells ........ total number of cells (acells*dcells*dups)\n");
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log("\n");
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log("A match containing the command 'attribute' followed by a list of space\n");
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log("separated 'name[=string_value]' values requires that the memory contains any\n");
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log("one of the given attribute name and string values (where specified), or name\n");
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log("and integer 1 value (if no string_value given, since Verilog will interpret\n");
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log("'(* attr *)' as '(* attr=1 *)').\n");
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log("A name prefixed with '!' indicates that the attribute must not exist.\n");
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log("\n");
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log("The interface for the created bram instances is derived from the bram\n");
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log("description. Use 'techmap' to convert the created bram instances into\n");
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log("instances of the actual bram cells of your target architecture.\n");
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@ -77,6 +77,26 @@ endbram
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# https://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf
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match $__XILINX_RAMB36_SDP
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attribute !ram_style
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attribute !logic_block
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min bits 1024
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min efficiency 5
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shuffle_enable B
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make_transp
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or_next_if_better
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endmatch
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match $__XILINX_RAMB36_SDP
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attribute ram_style=block ram_block
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attribute !logic_block
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shuffle_enable B
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make_transp
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or_next_if_better
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endmatch
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match $__XILINX_RAMB18_SDP
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attribute !ram_style
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attribute !logic_block
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min bits 1024
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min efficiency 5
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shuffle_enable B
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@ -85,6 +105,16 @@ match $__XILINX_RAMB36_SDP
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endmatch
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match $__XILINX_RAMB18_SDP
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attribute ram_style=block ram_block
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attribute !logic_block
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shuffle_enable B
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make_transp
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or_next_if_better
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endmatch
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match $__XILINX_RAMB36_TDP
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attribute !ram_style
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attribute !logic_block
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min bits 1024
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min efficiency 5
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shuffle_enable B
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@ -93,6 +123,16 @@ match $__XILINX_RAMB18_SDP
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endmatch
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match $__XILINX_RAMB36_TDP
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attribute ram_style=block ram_block
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attribute !logic_block
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shuffle_enable B
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make_transp
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or_next_if_better
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endmatch
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match $__XILINX_RAMB18_TDP
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attribute !ram_style
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attribute !logic_block
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min bits 1024
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min efficiency 5
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shuffle_enable B
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@ -101,8 +141,9 @@ match $__XILINX_RAMB36_TDP
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endmatch
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match $__XILINX_RAMB18_TDP
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min bits 1024
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min efficiency 5
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attribute ram_style=block ram_block
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attribute !logic_block
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shuffle_enable B
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make_transp
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endmatch
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88
tests/arch/common/memory_attributes/attributes_test.v
Normal file
88
tests/arch/common/memory_attributes/attributes_test.v
Normal file
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@ -0,0 +1,88 @@
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`default_nettype none
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module block_ram #(parameter DATA_WIDTH=4, ADDRESS_WIDTH=10)
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(input wire write_enable, clk,
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input wire [DATA_WIDTH-1:0] data_in,
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input wire [ADDRESS_WIDTH-1:0] address_in,
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output wire [DATA_WIDTH-1:0] data_out);
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localparam WORD = (DATA_WIDTH-1);
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localparam DEPTH = (2**ADDRESS_WIDTH-1);
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reg [WORD:0] data_out_r;
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reg [WORD:0] memory [0:DEPTH];
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always @(posedge clk) begin
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if (write_enable)
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memory[address_in] <= data_in;
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data_out_r <= memory[address_in];
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end
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assign data_out = data_out_r;
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endmodule // block_ram
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`default_nettype none
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module distributed_ram #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=4)
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(input wire write_enable, clk,
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input wire [DATA_WIDTH-1:0] data_in,
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input wire [ADDRESS_WIDTH-1:0] address_in,
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output wire [DATA_WIDTH-1:0] data_out);
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localparam WORD = (DATA_WIDTH-1);
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localparam DEPTH = (2**ADDRESS_WIDTH-1);
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reg [WORD:0] data_out_r;
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reg [WORD:0] memory [0:DEPTH];
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always @(posedge clk) begin
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if (write_enable)
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memory[address_in] <= data_in;
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data_out_r <= memory[address_in];
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end
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assign data_out = data_out_r;
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endmodule // distributed_ram
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`default_nettype none
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module distributed_ram_manual #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=4)
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(input wire write_enable, clk,
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input wire [DATA_WIDTH-1:0] data_in,
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input wire [ADDRESS_WIDTH-1:0] address_in,
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output wire [DATA_WIDTH-1:0] data_out);
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localparam WORD = (DATA_WIDTH-1);
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localparam DEPTH = (2**ADDRESS_WIDTH-1);
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reg [WORD:0] data_out_r;
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(* ram_style = "block" *) reg [WORD:0] memory [0:DEPTH];
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always @(posedge clk) begin
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if (write_enable)
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memory[address_in] <= data_in;
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data_out_r <= memory[address_in];
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end
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assign data_out = data_out_r;
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endmodule // distributed_ram
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`default_nettype none
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module distributed_ram_manual_syn #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=4)
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(input wire write_enable, clk,
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input wire [DATA_WIDTH-1:0] data_in,
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input wire [ADDRESS_WIDTH-1:0] address_in,
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output wire [DATA_WIDTH-1:0] data_out);
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localparam WORD = (DATA_WIDTH-1);
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localparam DEPTH = (2**ADDRESS_WIDTH-1);
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reg [WORD:0] data_out_r;
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(* synthesis, ram_block *) reg [WORD:0] memory [0:DEPTH];
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always @(posedge clk) begin
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if (write_enable)
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memory[address_in] <= data_in;
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data_out_r <= memory[address_in];
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end
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assign data_out = data_out_r;
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endmodule // distributed_ram
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47
tests/arch/xilinx/attributes_test.ys
Normal file
47
tests/arch/xilinx/attributes_test.ys
Normal file
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@ -0,0 +1,47 @@
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# Check that blockram memory without parameters is not modified
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read_verilog ../common/memory_attributes/attributes_test.v
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hierarchy -top block_ram
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synth_xilinx -top block_ram
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cd block_ram # Constrain all select calls below inside the top module
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select -assert-count 1 t:RAMB18E1
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# Check that distributed memory without parameters is not modified
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design -reset
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read_verilog ../common/memory_attributes/attributes_test.v
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hierarchy -top distributed_ram
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synth_xilinx -top distributed_ram
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cd distributed_ram # Constrain all select calls below inside the top module
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select -assert-count 8 t:RAM32X1D
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# Set ram_style distributed to blockram memory; will be implemented as distributed
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design -reset
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read_verilog ../common/memory_attributes/attributes_test.v
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prep
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setattr -mod -set ram_style "distributed" block_ram
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synth_xilinx -top block_ram
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cd block_ram # Constrain all select calls below inside the top module
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select -assert-count 32 t:RAM128X1D
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# Set synthesis, logic_block to blockram memory; will be implemented as distributed
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design -reset
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read_verilog ../common/memory_attributes/attributes_test.v
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prep
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setattr -mod -set logic_block 1 block_ram
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synth_xilinx -top block_ram
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cd block_ram # Constrain all select calls below inside the top module
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select -assert-count 0 t:RAMB18E1
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select -assert-count 32 t:RAM128X1D
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# Set ram_style block to a distributed memory; will be implemented as blockram
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design -reset
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read_verilog ../common/memory_attributes/attributes_test.v
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synth_xilinx -top distributed_ram_manual
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cd distributed_ram_manual # Constrain all select calls below inside the top module
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select -assert-count 1 t:RAMB18E1
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# Set synthesis, ram_block block to a distributed memory; will be implemented as blockram
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design -reset
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read_verilog ../common/memory_attributes/attributes_test.v
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synth_xilinx -top distributed_ram_manual_syn
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cd distributed_ram_manual_syn # Constrain all select calls below inside the top module
|
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select -assert-count 1 t:RAMB18E1
|
97
tests/arch/xilinx/blockram.ys
Normal file
97
tests/arch/xilinx/blockram.ys
Normal file
|
@ -0,0 +1,97 @@
|
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### TODO: Not running equivalence checking because BRAM models does not exists
|
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### currently. Checking instance counts instead.
|
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# Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1
|
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read_verilog ../common/blockram.v
|
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chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp
|
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synth_xilinx -top sync_ram_sdp
|
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cd sync_ram_sdp
|
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select -assert-count 1 t:RAMB18E1
|
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|
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design -reset
|
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read_verilog ../common/blockram.v
|
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chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 18 sync_ram_sdp
|
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synth_xilinx -top sync_ram_sdp
|
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cd sync_ram_sdp
|
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select -assert-count 1 t:RAMB18E1
|
||||
|
||||
design -reset
|
||||
read_verilog ../common/blockram.v
|
||||
chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp
|
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synth_xilinx -top sync_ram_sdp
|
||||
cd sync_ram_sdp
|
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select -assert-count 1 t:RAMB18E1
|
||||
|
||||
design -reset
|
||||
read_verilog ../common/blockram.v
|
||||
chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp
|
||||
synth_xilinx -top sync_ram_sdp
|
||||
cd sync_ram_sdp
|
||||
select -assert-count 1 t:RAMB18E1
|
||||
|
||||
# Anything memory bits < 1024 -> LUTRAM
|
||||
design -reset
|
||||
read_verilog ../common/blockram.v
|
||||
chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp
|
||||
synth_xilinx -top sync_ram_sdp
|
||||
cd sync_ram_sdp
|
||||
select -assert-count 0 t:RAMB18E1
|
||||
select -assert-count 4 t:RAM128X1D
|
||||
|
||||
# More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1
|
||||
design -reset
|
||||
read_verilog ../common/blockram.v
|
||||
chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp
|
||||
synth_xilinx -top sync_ram_sdp
|
||||
cd sync_ram_sdp
|
||||
select -assert-count 1 t:RAMB36E1
|
||||
|
||||
|
||||
### With parameters
|
||||
|
||||
design -reset
|
||||
read_verilog ../common/blockram.v
|
||||
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1
|
||||
setattr -set ram_style "block" m:memory
|
||||
synth_xilinx -top sync_ram_sdp
|
||||
cd sync_ram_sdp
|
||||
select -assert-count 1 t:RAMB18E1
|
||||
|
||||
design -reset
|
||||
read_verilog ../common/blockram.v
|
||||
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1
|
||||
setattr -set ram_block 1 m:memory
|
||||
synth_xilinx -top sync_ram_sdp
|
||||
cd sync_ram_sdp
|
||||
select -assert-count 1 t:RAMB18E1
|
||||
|
||||
design -reset
|
||||
read_verilog ../common/blockram.v
|
||||
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1
|
||||
setattr -set ram_style "dont_infer_a_ram_pretty_please" m:memory
|
||||
synth_xilinx -top sync_ram_sdp
|
||||
cd sync_ram_sdp
|
||||
select -assert-count 0 t:RAMB18E1
|
||||
|
||||
design -reset
|
||||
read_verilog ../common/blockram.v
|
||||
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1
|
||||
setattr -set logic_block 1 m:memory
|
||||
synth_xilinx -top sync_ram_sdp
|
||||
cd sync_ram_sdp
|
||||
select -assert-count 0 t:RAMB18E1
|
||||
|
||||
design -reset
|
||||
read_verilog ../common/blockram.v
|
||||
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 8 -chparam DATA_WIDTH 1
|
||||
setattr -set ram_style "block" m:memory
|
||||
synth_xilinx -top sync_ram_sdp
|
||||
cd sync_ram_sdp
|
||||
select -assert-count 1 t:RAMB18E1
|
||||
|
||||
design -reset
|
||||
read_verilog ../common/blockram.v
|
||||
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 8 -chparam DATA_WIDTH 1
|
||||
setattr -set ram_block 1 m:memory
|
||||
synth_xilinx -top sync_ram_sdp
|
||||
cd sync_ram_sdp
|
||||
select -assert-count 1 t:RAMB18E1
|
|
@ -1,47 +0,0 @@
|
|||
## TODO: Not running equivalence checking because BRAM models does not exists
|
||||
## currently. Checking instance counts instead.
|
||||
# Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1
|
||||
read_verilog ../common/blockram_params.v
|
||||
chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp
|
||||
synth_xilinx -top sync_ram_sdp
|
||||
cd sync_ram_sdp
|
||||
select -assert-count 1 t:RAMB18E1
|
||||
|
||||
design -reset
|
||||
read_verilog ../common/blockram_params.v
|
||||
chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 18 sync_ram_sdp
|
||||
synth_xilinx -top sync_ram_sdp
|
||||
cd sync_ram_sdp
|
||||
select -assert-count 1 t:RAMB18E1
|
||||
|
||||
design -reset
|
||||
read_verilog ../common/blockram_params.v
|
||||
chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp
|
||||
synth_xilinx -top sync_ram_sdp
|
||||
cd sync_ram_sdp
|
||||
select -assert-count 1 t:RAMB18E1
|
||||
|
||||
design -reset
|
||||
read_verilog ../common/blockram_params.v
|
||||
chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp
|
||||
synth_xilinx -top sync_ram_sdp
|
||||
cd sync_ram_sdp
|
||||
select -assert-count 1 t:RAMB18E1
|
||||
|
||||
# Anything memory bits < 1024 -> LUTRAM
|
||||
design -reset
|
||||
read_verilog ../common/blockram_params.v
|
||||
chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp
|
||||
synth_xilinx -top sync_ram_sdp
|
||||
cd sync_ram_sdp
|
||||
select -assert-count 0 t:RAMB18E1
|
||||
select -assert-count 4 t:RAM128X1D
|
||||
|
||||
# More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1
|
||||
design -reset
|
||||
read_verilog ../common/blockram_params.v
|
||||
chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp
|
||||
synth_xilinx -top sync_ram_sdp
|
||||
cd sync_ram_sdp
|
||||
select -assert-count 1 t:RAMB36E1
|
||||
|
Loading…
Reference in a new issue