mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-05-12 02:04:44 +00:00
Code Activity
4859 commits 118 branches 54 tags 57 MiB
Commit graph

671 commits

Author SHA1 Message Date
Eddie Hung
d7f0700bae Convert to use #945 2019-04-21 15:19:02 -07:00
Eddie Hung
caec7f9d2c Merge remote-tracking branch 'origin/master' into xaig 2019-04-20 12:23:49 -07:00
Eddie Hung
af4652522f ABC_FLOPS -> ABC_MODEL -- only whitebox if ABC_MODEL set 2019-04-19 21:09:55 -07:00
Eddie Hung
2776925bcf Make SB_DFF whitebox 2019-04-19 08:36:38 -07:00
Eddie Hung
19b660ff6e Fix SB_DFF comb model 2019-04-18 23:07:16 -07:00
Eddie Hung
0919f36b88 Missing close bracket 2019-04-18 17:50:11 -07:00
Eddie Hung
cf66416110 Annotate SB_DFF* with abc_flop and abc_box_id 2019-04-18 17:46:53 -07:00
Eddie Hung
ca1eb98a97 Add SB_DFF* to boxes 2019-04-18 17:46:32 -07:00
Eddie Hung
4c327cf316 Use new -wb flag for ABC flow 2019-04-18 10:32:41 -07:00
Eddie Hung
9278192efe Also update Makefile.inc 2019-04-18 09:58:34 -07:00
Eddie Hung
7b6ab937c1 Make SB_LUT4 a blackbox 2019-04-18 09:05:22 -07:00
Eddie Hung
8024f41897 Fix rename 2019-04-18 09:04:34 -07:00
Eddie Hung
ed5e75ed7d Rename to abc_*.{box,lut} 2019-04-18 09:02:58 -07:00
Eddie Hung
6008bb7002 Revert "synth_* with -retime option now calls abc with -D 1 as well" 
This reverts commit 9a6da9a79a.
 2019-04-18 07:59:16 -07:00
Eddie Hung
0642baabbc Merge branch 'master' into eddie/fix_retime 2019-04-18 07:57:17 -07:00
Eddie Hung
8fd455c910 Update Makefile.inc too 2019-04-17 15:19:48 -07:00
Eddie Hung
c795e14d25 Reduce to three devices: hx, lp, u 2019-04-17 15:19:02 -07:00
Eddie Hung
5c0853fc51 Add up5k timings 2019-04-17 15:10:39 -07:00
Eddie Hung
4b520ae627 Fix grammar 2019-04-17 15:10:22 -07:00
Eddie Hung
3105a8a653 Update error message 2019-04-17 15:07:44 -07:00
Eddie Hung
6f3e5297db Add "-device" argument to synth_ice40 2019-04-17 15:04:46 -07:00
Eddie Hung
671cca59a9 Missing abc_flop_q attribute on SPRAM 2019-04-17 14:44:08 -07:00
Eddie Hung
437fec0d88 Map to SB_LUT4 from fastest input first 2019-04-17 13:01:17 -07:00
Eddie Hung
58847df1b9 Mark seq output ports with "abc_flop_q" attr 2019-04-17 12:27:45 -07:00
Eddie Hung
1eade06671 Also update Makefile.inc 2019-04-17 12:27:02 -07:00
Eddie Hung
4fb9ccfcd8 synth_ice40 to use renamed files 2019-04-17 12:22:03 -07:00
Eddie Hung
42c33db22c Rename to abc.* 2019-04-17 12:15:34 -07:00
Eddie Hung
c1ebe51a75 Revert "Try using an ICE40_CARRY_LUT primitive to avoid ABC issues" 
This reverts commit a7632ab332.
 2019-04-17 11:10:20 -07:00
Eddie Hung
a7632ab332 Try using an ICE40_CARRY_LUT primitive to avoid ABC issues 2019-04-17 11:10:04 -07:00
Eddie Hung
17fb6c3522 Fix spacing 2019-04-17 08:40:50 -07:00
Eddie Hung
743c164eee Add SB_LUT4 to box library 2019-04-16 17:34:11 -07:00
Eddie Hung
7980118d74 Add ice40 box files 2019-04-16 16:39:30 -07:00
Eddie Hung
04e466d5e4 Add support for synth_xilinx -abc9 and ignore abc9 -dress opt 2019-04-12 12:28:37 -07:00
Eddie Hung
f77da46a87 Merge remote-tracking branch 'origin/master' into xaig 2019-04-12 12:21:48 -07:00
Eddie Hung
db1a5ec6a2
Merge pull request #928 from litghost/add_xc7_sim_models 
Add additional cells sim models for core 7-series primitives.
 2019-04-12 11:52:45 -07:00
Keith Rothman
1f9235ede5 Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-04-12 09:35:15 -07:00
Diego
643ae9bfc5 Fixing issues in CycloneV cell sim 2019-04-11 19:59:03 -05:00
Eddie Hung
9a6da9a79a synth_* with -retime option now calls abc with -D 1 as well 2019-04-10 08:32:53 -07:00
Keith Rothman
e107ccdde8 Fix LUT6_2 definition. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-04-09 11:43:19 -07:00
Keith Rothman
5e0339855f Add additional cells sim models for core 7-series primatives. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-04-09 09:01:53 -07:00
Eddie Hung
bca3cf6843 Merge branch 'master' into xaig 2019-04-08 16:31:59 -07:00
Eddie Hung
9758701574 Move techamp t:$_DFF_?N? to before abc call 2019-04-05 15:39:05 -07:00
Eddie Hung
23a6533e98 Retry 2019-04-05 15:31:54 -07:00
Eddie Hung
8b6085254a Resolve @daveshah1 comment, update synth_xilinx help 2019-04-05 15:15:13 -07:00
Eddie Hung
ff0912c75e synth_xilinx to techmap FFs after abc call, otherwise -retime fails 2019-04-05 14:43:06 -07:00
David Shah
46f6a60d58 xilinx: Add keep attribute where appropriate 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-22 13:57:17 +00:00
Clifford Wolf
fe1fb1336b Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-19 20:30:28 +01:00
Clifford Wolf
9284cf92b8 Remove ice40/cells_sim.v hack to avoid warning for blocking memory writes 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-12 20:14:18 +01:00
Clifford Wolf
ff4c2a14ae Fix typo in ice40_braminit help msg 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-09 13:24:55 -08:00
Clifford Wolf
2ace1b0041
Merge pull request #859 from smunaut/ice40_braminit 
iCE40 BRAM primitives init from file
 2019-03-09 13:24:10 -08:00