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									 Eddie Hung | 5ebdc0f8e0 | Merge pull request #1638 from YosysHQ/eddie/fix1631 clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_* | 2020-02-05 19:31:18 +01:00 |  | 
				
					
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									 Eddie Hung | 2245afa142 | More rigorous test | 2020-01-16 09:15:42 -08:00 |  | 
				
					
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									 Eddie Hung | e30b6bbbf8 | clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_* | 2020-01-15 09:51:31 -08:00 |  | 
				
					
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									 Eddie Hung | 4a80510877 | Even more obvious testcase | 2019-12-11 23:52:05 -08:00 |  | 
				
					
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									 Eddie Hung | 61a1f3f49b | Make testcase clearer with \o having its own init | 2019-12-11 23:48:09 -08:00 |  | 
				
					
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									 Eddie Hung | e75ca29b19 | Add test: 'Warning: ignoring initial value on non-register: \o' | 2019-12-11 11:26:54 -08:00 |  | 
				
					
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									 Eddie Hung | 3fb604c75d | Revert "Add test that is expecting to fail" This reverts commit c28d4b8047. | 2019-10-08 12:41:26 -07:00 |  | 
				
					
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									 Eddie Hung | c28d4b8047 | Add test that is expecting to fail | 2019-10-02 14:52:40 -07:00 |  | 
				
					
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									 Eddie Hung | 00387f3927 | Revert to using clean | 2019-08-27 09:24:32 -07:00 |  | 
				
					
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									 Eddie Hung | dc87372a97 | Wire with init on FF part, 1'bx on non-FF part | 2019-08-24 15:05:44 -07:00 |  | 
				
					
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									 Eddie Hung | 10c41a5cf5 | Blocking assignment | 2019-08-23 09:11:04 -07:00 |  | 
				
					
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									 Eddie Hung | 51ffb093b5 | In sat: 'x' in init attr should not override constant | 2019-08-22 16:43:08 -07:00 |  | 
				
					
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									 Zachary Snow | 5855024ccc | support repeat loops with constant repeat counts outside of constant functions | 2019-04-09 12:28:32 -04:00 |  | 
				
					
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									 Clifford Wolf | dbfd8460a9 | Allow $size and $bits in verilog mode, actually check test case | 2017-09-29 11:56:43 +02:00 |  | 
				
					
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									 Clifford Wolf | 8836943693 | Added yet another resource sharing test case | 2014-07-20 21:15:01 +02:00 |  | 
				
					
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									 Clifford Wolf | 3b52121d32 | now ignore init attributes on non-register wires in sat command | 2014-07-05 11:18:38 +02:00 |  | 
				
					
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									 Clifford Wolf | 482d9208aa | Added read_verilog -sv options, added support for bit, logic, allways_ff, always_comb, and always_latch | 2014-06-12 11:54:20 +02:00 |  | 
				
					
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									 Clifford Wolf | 039bb456cc | Added test cases for expose -evert-dff | 2014-02-08 21:31:56 +01:00 |  | 
				
					
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									 Clifford Wolf | 244e8ce1f4 | Added splice command | 2014-02-07 20:30:56 +01:00 |  | 
				
					
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									 Clifford Wolf | 849fd62cfe | Added counters sat test case | 2014-02-06 01:00:56 +01:00 |  | 
				
					
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									 Clifford Wolf | 7a66b38c3e | Added test cases for sat command | 2014-02-04 13:43:34 +01:00 |  |