Miodrag Milanović
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637650597b
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Merge pull request #2059 from boqwxp/logger-vector-to-dict
log: Use `dict` instead of `std::vector<std::pair>` for `log_expect_{error, warning, log}` to better express the intent that each element is unique.
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2020-05-21 15:36:30 +02:00 |
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N. Engelhardt
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026fed3135
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Merge pull request #2046 from PeterCrozier/trap
Extend YS_DEBUGTRAP to MacOS.
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2020-05-20 10:12:24 +02:00 |
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N. Engelhardt
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7c4e580f8f
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Merge pull request #2054 from boqwxp/fix-smtbmc
smtbmc: Fix return status handling.
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2020-05-20 08:55:36 +02:00 |
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Alberto Gonzalez
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6eea4b3d79
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kernel: Try an order-independent approach to hashing dict.
Co-Authored-By: David Shah <dave@ds0.me>
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
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2020-05-19 23:32:53 +00:00 |
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Alberto Gonzalez
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1053032a81
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smtbmc: Fix typo in error message.
Co-Authored-By: N. Engelhardt <nak@symbioticeda.com>
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2020-05-19 16:13:44 +00:00 |
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Martin
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ae887c49f9
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Merge branch 'master' of https://github.com/hackfin/yosys
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2020-05-19 11:14:51 +02:00 |
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Martin
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43c34a7828
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idict handling in wrapper
- Also, re-applied no-line-break workaround to rtlil.h to make parser
catch all methods.
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2020-05-19 11:13:49 +02:00 |
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Marcelina Kościelnicka
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aee439360b
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Add force_downto and force_upto wire attributes.
Fixes #2058.
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2020-05-19 01:42:40 +02:00 |
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Eddie Hung
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2d573a0ff6
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Merge pull request #1926 from YosysHQ/eddie/abc9_auto_dff
abc9: support seq synthesis when module has (* abc9_flop *) and bypass non-combinatorial (* abc9_box *)
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2020-05-18 08:06:50 -07:00 |
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Alberto Gonzalez
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049e4caceb
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firrtl: Accept techmapped cell types in FIRRTL backend.
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2020-05-17 10:03:11 +00:00 |
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Claire Wolf
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fa8cb3e35d
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Revert "Add support for non-power-of-two mem chunks in verific importer"
This reverts commit 173aa27ca5.
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2020-05-17 11:31:11 +02:00 |
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Eddie Hung
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39fa1e160d
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verific: rewrite initial assume/asserts prior to elaboration
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2020-05-15 14:05:28 -07:00 |
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Alberto Gonzalez
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8297afe925
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log: Use dict instead of std::vector<std::pair> for log_expect_{error, warning, log} to better express the intent that each element is unique.
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2020-05-15 00:55:32 +00:00 |
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Eddie Hung
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67fc0c3698
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abc9: use (* abc9_keep *) instead of (* abc9_scc *); apply to $_DFF_?_
instead of moving them to $__ prefix
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2020-05-14 16:44:35 -07:00 |
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Eddie Hung
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7101ef550b
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verilog: attributes before task enable (but 13 s/r conflicts)
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2020-05-14 16:10:11 -07:00 |
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Eddie Hung
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e7fd8912f0
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tests: attributes before task enable
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2020-05-14 16:09:41 -07:00 |
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Eddie Hung
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07eecff9cc
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Merge pull request #2055 from YosysHQ/eddie/logger_multiple
logger: fix for multiple calls with same pattern
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2020-05-14 15:30:08 -07:00 |
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Alberto Gonzalez
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976edb7597
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kernel: Ensure dict always hashes to the same value given the same contents.
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2020-05-14 20:06:55 +00:00 |
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Alberto Gonzalez
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35b94d1f66
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kernel: Re-implement dict hash code as a dict member function instead of a specialized template for hash_ops.
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2020-05-14 20:06:55 +00:00 |
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Alberto Gonzalez
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e173291649
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techmap: Replace naughty const_cast<>()s.
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
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2020-05-14 20:06:55 +00:00 |
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Alberto Gonzalez
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97fd304cbe
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techmap: Replace pseudo-private member usage with the range accessor function and some naughty const_cast<>()s.
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2020-05-14 20:06:55 +00:00 |
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Eddie Hung
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36bb201dd9
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techmap: sort celltypeMap as it determines techmap order
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2020-05-14 20:06:55 +00:00 |
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Alberto Gonzalez
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ce62d0751a
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Replace std::sets using custom comparators with pool.
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
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2020-05-14 20:06:55 +00:00 |
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Eddie Hung
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dabeb1e8a1
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techmap: prefix special wires with backslash for use as IdString
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2020-05-14 20:06:55 +00:00 |
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Alberto Gonzalez
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bd54d67ad4
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Further clean up passes/techmap/techmap.cc.
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
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2020-05-14 20:06:54 +00:00 |
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Alberto Gonzalez
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982562ff13
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Use emplace() for more efficient insertion into various dicts.
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2020-05-14 20:06:54 +00:00 |
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Alberto Gonzalez
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c658d9d59d
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Build constant bits directly rather than constructing an object and copying its bits.
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2020-05-14 20:06:54 +00:00 |
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Alberto Gonzalez
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f235f212ea
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Replace std::set with pool for cell_to_inbit and outbit_to_cell.
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2020-05-14 20:06:54 +00:00 |
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Alberto Gonzalez
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6294621825
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Use emplace() rather than insert().
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2020-05-14 20:06:54 +00:00 |
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Alberto Gonzalez
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dfcb936cd5
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Clean up pseudo-private member usage and ensure range iteration uses references where possible to avoid unnecessary copies.
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2020-05-14 20:06:54 +00:00 |
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Alberto Gonzalez
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a4755c50c3
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Clean up extraneous buffer.
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2020-05-14 20:06:54 +00:00 |
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Alberto Gonzalez
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7857782575
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Replace std::map with dict for unique_bit_id.
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2020-05-14 20:06:54 +00:00 |
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Alberto Gonzalez
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6d64d768b0
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Replace std::map with dict for port_new2old_map, port_connmap, and cellbits_to_tplbits.
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2020-05-14 20:06:54 +00:00 |
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Alberto Gonzalez
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5cb4ae4666
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Replace std::map with dict for connbits_map, cell_to_inbit, and outbit_to_cell.
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2020-05-14 20:06:54 +00:00 |
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Alberto Gonzalez
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c43017fc08
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Replace std::map with dict for TechmapWires type.
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2020-05-14 20:06:54 +00:00 |
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Alberto Gonzalez
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644e55b3d3
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Replace std::map with dict for celltypeMap.
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2020-05-14 20:06:53 +00:00 |
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Alberto Gonzalez
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67f4046c05
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Replace std::set with pool for handled_cells and techmap_wire_names.
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2020-05-14 20:06:53 +00:00 |
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Alberto Gonzalez
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64c16f8c13
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Replace std::map with dict for positional_ports.
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2020-05-14 20:06:53 +00:00 |
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Alberto Gonzalez
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2fb4931e5b
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Add specialized hash() for type dict and use a dict instead of a std::map for techmap_cache and techmap_do_cache.
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2020-05-14 20:06:53 +00:00 |
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Alberto Gonzalez
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437f3fb342
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Replace std::map with dict for simplemap_mappers.
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2020-05-14 20:06:53 +00:00 |
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Alberto Gonzalez
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99b586b283
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Use nullptr instead of NULL in passes/techmap/techmap.cc.
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2020-05-14 20:06:53 +00:00 |
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Alberto Gonzalez
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5f7f213c7f
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Replace std::string and RTLIL::IdString with IdString in passes/techmap/techmap.cc.
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
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2020-05-14 20:06:53 +00:00 |
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Alberto Gonzalez
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e49fdee404
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Do not modify design modules while iterating over modules().
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
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2020-05-14 20:06:53 +00:00 |
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Alberto Gonzalez
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985a29ff3b
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Clean up pseudo-private member usage, superfluous std::vector instantiation, and RTLIL::id2cstr() usage in passes/techmap/techmap.cc.
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2020-05-14 20:06:53 +00:00 |
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Eddie Hung
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7b3a4a1fff
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opt_expr: Sx to Sz; spotted by @Xiretza
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2020-05-14 12:14:23 -07:00 |
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Eddie Hung
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73b7ea713c
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Merge pull request #1994 from YosysHQ/eddie/fix_bug1758
opt_expr: improve single-bit $and/$or/$xor/$xnor cells; gate cells too
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2020-05-14 11:56:22 -07:00 |
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Eddie Hung
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425867d175
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logger: clean up doc
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2020-05-14 10:38:31 -07:00 |
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Eddie Hung
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02df0198b6
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abc9_ops: -prep_hier to create unmap module that removes Q's (* init *)
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2020-05-14 10:33:57 -07:00 |
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Eddie Hung
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13f9d65b6f
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abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove it
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2020-05-14 10:33:57 -07:00 |
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Eddie Hung
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fa31e84112
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Fix broken test when ignoring abc9_flop with init == 1'b1
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2020-05-14 10:33:57 -07:00 |
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