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14552 commits 91 branches 52 tags 61 MiB
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2414 commits

Author SHA1 Message Date
Miodrag Milanovic 14e43139cb Run opt_merge, helps with inverted reset/load signals 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 220ddeac4d Set -mince and -minsrst 2024-08-15 17:50:36 +02:00
Miodrag Milanovic dbf1d037e8 Cleanup 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 7bf623a0c7 Fix simulation model warnings 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 262ad03cd3 Add iopads by default add option to disable and keep old one for compatibility 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 8f806c0d12 Added DDFR support 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 1a6e5c671f Add meminit handling for NX_RFB_U 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 6876a27547 Add NX_DFR simulation model 2024-08-15 17:50:36 +02:00
Miodrag Milanovic eb30be6189 Impulse does not support these types but NG-ULTRA architecture does 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 7601dc740b Some memory types are only supported on NG-LARGE 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 4372487a6f raw must be 16 bits for nx tools to work 2024-08-15 17:50:36 +02:00
Miodrag Milanovic f8ae93c0ea run setundef for all x inputs 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 40f05009e3 Fix CY chaining and CI injection 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 596506b88b Add NX_XCDC_U to wrappers 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 8909a42796 Better wire check 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 5766555642 Support brams with initialization 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 4aaab8f395 start adding wfg model 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 41a86fdb2c fix 2024-08-15 17:50:36 +02:00
Miodrag Milanovic f4d8ea4c40 Start adding RFB simulation models 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 8eb099c1f4 remove debug attribute 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 829dd62054 block ram mapping for standard modes 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 9d6b47466f Add RF initialization 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 7e4aef06e4 Add register file mapping 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 11449ec493 Cleanup not connected ports 2024-08-15 17:50:36 +02:00
Miodrag Milanovic f9f68c3cd1 Split sim models into multiple files and implement few 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 04d3672121 No need for LOC 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 41ae513d60 support other I/O configurations 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 645888cff5 cleanup 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 9a9190b67d enable dff context initialization 2024-08-15 17:50:36 +02:00
Miodrag Milanovic dc16bdd85b DFF reset and context must be in sync 2024-08-15 17:50:36 +02:00
Miodrag Milanovic cb45f8b69d Fixed of mapping and initialization 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 198fc963ca Add new DFF types, and added "-nodffe" option 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 0c4bbf7e4b Fix existing DFF mapping and add new types 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 94675a5e0b Fix dff simulation model 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 606439b44c do not leave NX_RAM empty to prevent removing it 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 4cb8e62626 Properly map ff ram 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 1591d258a9 Made NX_CY model more robust 2024-08-15 17:50:36 +02:00
Miodrag Milanovic dac4f04460 add latch mapping, and remove aldff for now 2024-08-15 17:50:36 +02:00
Miodrag Milanovic cf21b48bfd fix co on nx_cy 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 31f943513b set add_carry property and all inputs to 0 2024-08-15 17:50:36 +02:00
Miodrag Milanovic b6f7383736 break long chains 2024-08-15 17:50:36 +02:00
Miodrag Milanovic ab32dde81b optimized 2024-08-15 17:50:36 +02:00
Miodrag Milanovic da6a62f3a0 Initial carry chain handling pass 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 474ed28aee added no-rw-check, and new rfb models 2024-08-15 17:50:36 +02:00
Miodrag Milanovic a5bfb23b47 start cleaning rams 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 370517b1e6 IO 2024-08-15 17:50:36 +02:00
Miodrag Milanovic fa14c600ff commented remainder of primitives 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 8023f921e3 RAM 2024-08-15 17:50:36 +02:00
Miodrag Milanovic b202126c76 IOM 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 71f0984dc9 fixes 2024-08-15 17:50:36 +02:00
Miodrag Milanovic ef15325dce removed virtual primitive 2024-08-15 17:50:36 +02:00
Miodrag Milanovic f836de6bcc mark DSPs as TODOs for now 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 8f42d6dace fifo 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 012f0e2952 memory blocks 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 3ed5ea24b2 sortout more blackboxes 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 0ecc2e597f PLLs 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 200e1a7bfe more DSP wrappers 2024-08-15 17:50:36 +02:00
Miodrag Milanovic ce635abc21 NX_DSP/SPLIT 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 60611b936b CDC_U 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 815622f685 CDC_L wrappers 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 827ea11503 start splitting blackboxes and add wrapper techmap 2024-08-15 17:50:36 +02:00
Miodrag Milanovic cfce7dd2f8 remove soc 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 9700971a8a just copy LOC 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 989eef29b2 produce less cells 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 74289b7339 remove init from sdff 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 4c1f84a686 add io mapping 2024-08-15 17:50:36 +02:00
Lofty b0c4add642 Added lutram 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 5d898ab223 Add blackboxes 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 8374f0336d add family and ability to disable carry chains 2024-08-15 17:50:36 +02:00
Lofty b3f59c9820 Add NX_CY 2024-08-15 17:50:36 +02:00
Lofty b4e9bb0d85 Add FFs and related tests 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 94b6f19cf0 Make lut init match vendor tools 2024-08-15 17:50:36 +02:00
Lofty 3b48e9df61 Add initial NanoXplore pass 2024-08-15 17:50:36 +02:00
N. Engelhardt 9f869b265c
Merge pull request #4474 from tony-min-1/mchp 
Add PolarFire FPGA support
 2024-07-29 15:28:44 +02:00
Emil J 43c1328fbb
Merge pull request #4479 from yrabbit/z1-power 
Gowin. Add an energy saving primitive
 2024-07-18 11:56:00 +02:00
YRabbit 19bbdd8800 Gowin. Add the DCS primitive 
Not so much adding the primitive itself, but only its DCS_MODE
parameter, without which an error occurs.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2024-07-11 21:39:44 +10:00
chunlin min 3db69b7a10 inline all tests. Add switch to remove init values as PolarFire DFFs do not support init 2024-07-08 17:03:03 -04:00
chunlin min 0afb5e28fb cosmetic changes 2024-07-08 15:10:44 -04:00
chunlin min af67c745c4 initialize argidx to 1 2024-07-08 11:41:41 -04:00
chunlin min a0c9d10118 undo last change, to investigate dff_opt test failure 2024-07-08 11:30:52 -04:00
chunlin min 3c95a28dc2 fix compile warning 2024-07-08 11:13:53 -04:00
Tony Min d41688f7d7
Revisions (#4) 
* area should be 1 for all LUTs

* clean up macros

* add log_assert to fail noisily when encountering oddly configured DFF

* clean help msg

* flatten set to true by default

* update

* merge mult tests

* remove redundant test

* move all dsp tests to single file and remove redundant tests

* update ram tests

* add more dff tests

* fix c++20 compile errors

* add option to dump verilog

* default to use abc9

* remove -abc9 option since its the default now

---------

Co-authored-by: tony <minchunlin@gmail.com>
 2024-07-08 10:57:16 -04:00
YRabbit 9d0bca9775 Gowin. Add an energy saving primitive 
We add a BANDGAP primitive used to turn off power to OSC, PLL and other
things on some GOWIN chips.

We also mark this primitive and GSR as keep.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2024-07-06 18:58:21 +10:00
Tony Min 6fe0e00050
Add missing u sram init (#3) 
add missing INIT for uSRAM
 2024-07-04 16:39:10 -04:00
chunlin min 8e7ec2d660 add assertions for synth_microchip tests 2024-07-04 15:45:44 -04:00
chunlin min e3c4791e5b move microchip tests from techlibs/microchip/tests to tests/arch/microchip 2024-07-04 14:16:52 -04:00
chunlin min 19d3214861 use output reg instead of additional reg declaration 2024-07-04 14:13:26 -04:00
C77874 5ba06fd947 another typo 2024-07-04 10:33:59 -07:00
C77874 6b80e02d62 missed a few pf instances 2024-07-04 10:25:15 -07:00
C77874 c385421c17 rename options 2024-07-04 09:45:04 -07:00
C77874 d0cd01adfe fixed typos, build with makefile succeeds 2024-07-04 09:33:58 -07:00
C77874 59e45be275 Merge branch 'mchp' of https://github.com/tony-min-1/yosys into change_filenames 2024-07-04 09:00:38 -07:00
C77874 0bb7d1373f changes made to filenames + references 2024-07-04 08:53:41 -07:00
Chun Lin Min 7770fa70e1 fix cells_sim.v 2024-07-04 05:20:22 -07:00
Chun Lin Min f57b624281 fix indent 2024-07-02 13:54:36 -07:00
Chun Lin Min 68a11c9941 more indent fix 2024-07-02 13:51:48 -07:00
Chun Lin Min 2ced2752e9 replace space indent with tab indent 2024-07-02 13:47:18 -07:00
Chun Lin Min acddc36389 add PolarFire FPGA support 2024-07-02 12:44:30 -07:00
Lofty 8cc9aa7fc6 intel_alm: drop quartus support 2024-05-03 11:32:33 +01:00
KrystalDelusion c3ae33da33
Merge pull request #4285 from YosysHQ/typo_fixup 
Typo fixing
 2024-04-25 09:54:48 +12:00