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https://github.com/YosysHQ/yosys
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start cleaning rams
This commit is contained in:
Miodrag Milanovic
parent
370517b1e6
commit
a5bfb23b47
8 changed files with 101 additions and 27 deletions
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@ -3,6 +3,8 @@ OBJS += techlibs/nanoxplore/synth_nanoxplore.o
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# Techmap
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$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/arith_map.v))
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$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/brams_map.v))
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$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/brams.txt))
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$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb.v))
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$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb_l.v))
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$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb_m.v))
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@ -13,5 +15,6 @@ $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap.v))
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$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_l.v))
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$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_m.v))
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$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_u.v))
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$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/drams.txt))
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$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/io_map.v))
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$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_map_u.v))
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$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_u.txt))
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26
techlibs/nanoxplore/brams.txt
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26
techlibs/nanoxplore/brams.txt
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@ -0,0 +1,26 @@
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ram block $__NX_RAM_ {
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abits 13;
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widths 1 2 4 9 per_port;
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cost 64;
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init no_undef;
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port srsw "A" "B" {
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clock anyedge;
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clken;
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portoption "WRITEMODE" "NORMAL" {
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rdwr no_change;
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}
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portoption "WRITEMODE" "WRITETHROUGH" {
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rdwr new;
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}
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portoption "WRITEMODE" "READBEFOREWRITE" {
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rdwr old;
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}
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option "RESETMODE" "SYNC" {
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rdsrst zero ungated block_wr;
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}
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option "RESETMODE" "ASYNC" {
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rdarst zero;
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}
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rdinit zero;
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}
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}
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32
techlibs/nanoxplore/brams_map.v
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32
techlibs/nanoxplore/brams_map.v
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@ -0,0 +1,32 @@
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module $__NX_RAM_ (...);
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parameter INIT = 0;
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parameter OPTION_RESETMODE = "SYNC";
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parameter PORT_A_WIDTH = 9;
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parameter PORT_A_CLK_POL = 1;
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parameter PORT_A_OPTION_WRITEMODE = "NORMAL";
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input PORT_A_CLK;
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input PORT_A_CLK_EN;
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input PORT_A_WR_EN;
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input PORT_A_RD_SRST;
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input PORT_A_RD_ARST;
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input [12:0] PORT_A_ADDR;
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input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;
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output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;
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parameter PORT_B_WIDTH = 9;
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parameter PORT_B_CLK_POL = 1;
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parameter PORT_B_OPTION_WRITEMODE = "NORMAL";
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input PORT_B_CLK;
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input PORT_B_CLK_EN;
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input PORT_B_WR_EN;
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input PORT_B_RD_SRST;
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input PORT_B_RD_ARST;
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input [12:0] PORT_B_ADDR;
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input [PORT_B_WIDTH-1:0] PORT_B_WR_DATA;
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output [PORT_B_WIDTH-1:0] PORT_B_RD_DATA;
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endmodule
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@ -70,15 +70,3 @@ module \$_SDFF_NP1_ (input D, C, R, output Q);
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wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
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NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b1), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b1), .dff_type(1'b1)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b0), .R(R), .O(Q));
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endmodule
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module $__NX_XRFB_64x18_ (input PORT_W_CLK, input [5:0] PORT_W_ADDR, PORT_R_ADDR, input [17:0] PORT_W_WR_DATA, input PORT_W_WR_EN, output [17:0] PORT_R_RD_DATA);
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parameter INIT = 1152'bx;
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parameter PORT_W_CLK_POL = 1'b1;
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NX_XRFB_64x18 #(.mem_ctxt(INIT), .wck_edge(~PORT_W_CLK_POL)) _TECHMAP_REPLACE_ (.WCK(PORT_W_CLK), .I(PORT_W_WR_DATA), .RA(PORT_R_ADDR), .WA(PORT_W_ADDR), .WE(PORT_W_WR_EN), .WEA(1'b1), .O(PORT_R_RD_DATA));
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endmodule
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module $__NX_XRFB_32x36_ (input PORT_W_CLK, input [4:0] PORT_W_ADDR, PORT_R_ADDR, input [35:0] PORT_W_WR_DATA, input PORT_W_WR_EN, output [35:0] PORT_R_RD_DATA);
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parameter INIT = 1152'bx;
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parameter PORT_W_CLK_POL = 1'b1;
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NX_XRFB_32x36 #(.mem_ctxt(INIT), .wck_edge(~PORT_W_CLK_POL)) _TECHMAP_REPLACE_ (.WCK(PORT_W_CLK), .I(PORT_W_WR_DATA), .RA(PORT_R_ADDR), .WA(PORT_W_ADDR), .WE(PORT_W_WR_EN), .WEA(1'b1), .O(PORT_R_RD_DATA));
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endmodule
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12
techlibs/nanoxplore/rf_rams_map_u.v
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12
techlibs/nanoxplore/rf_rams_map_u.v
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@ -0,0 +1,12 @@
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module $__NX_XRFB_64x18_ (input PORT_W_CLK, input [5:0] PORT_W_ADDR, PORT_R_ADDR, input [17:0] PORT_W_WR_DATA, input PORT_W_WR_EN, output [17:0] PORT_R_RD_DATA);
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parameter INIT = 1152'bx;
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parameter PORT_W_CLK_POL = 1'b1;
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NX_XRFB_64x18 #(.mem_ctxt(INIT), .wck_edge(~PORT_W_CLK_POL)) _TECHMAP_REPLACE_ (.WCK(PORT_W_CLK), .I(PORT_W_WR_DATA), .RA(PORT_R_ADDR), .WA(PORT_W_ADDR), .WE(PORT_W_WR_EN), .WEA(1'b1), .O(PORT_R_RD_DATA));
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endmodule
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module $__NX_XRFB_32x36_ (input PORT_W_CLK, input [4:0] PORT_W_ADDR, PORT_R_ADDR, input [35:0] PORT_W_WR_DATA, input PORT_W_WR_EN, output [35:0] PORT_R_RD_DATA);
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parameter INIT = 1152'bx;
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parameter PORT_W_CLK_POL = 1'b1;
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NX_XRFB_32x36 #(.mem_ctxt(INIT), .wck_edge(~PORT_W_CLK_POL)) _TECHMAP_REPLACE_ (.WCK(PORT_W_CLK), .I(PORT_W_WR_DATA), .RA(PORT_R_ADDR), .WA(PORT_W_ADDR), .WE(PORT_W_WR_EN), .WEA(1'b1), .O(PORT_R_RD_DATA));
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endmodule
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@ -73,11 +73,11 @@ struct SynthNanoXplorePass : public ScriptPass
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log(" -nocy\n");
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log(" do not map adders to CY cells\n");
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log("\n");
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log(" -nolutram\n");
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log(" do not use LUT RAM cells in output netlist\n");
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log(" -norfram\n");
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log(" do not use Register File RAM cells in output netlist\n");
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log("\n");
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log(" -nobram\n");
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log(" do not use block RAM cells in output netlist\n");
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log(" do not use block NX_RAM cells in output netlist\n");
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log("\n");
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log(" -nodsp\n");
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log(" do not map multipliers to NX_DSP cells\n");
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@ -92,8 +92,8 @@ struct SynthNanoXplorePass : public ScriptPass
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}
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string top_opt, json_file, family;
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bool flatten, abc9, nocy, nolutram, nobram, nodsp, iopad;
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std::string postfix;
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bool flatten, abc9, nocy, norfram, nobram, nodsp, iopad;
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std::string postfix, rf_postfix;
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void clear_flags() override
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{
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@ -103,11 +103,12 @@ struct SynthNanoXplorePass : public ScriptPass
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flatten = true;
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abc9 = false;
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nocy = false;
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nolutram = false;
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norfram = false;
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nobram = false;
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nodsp = false;
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iopad = false;
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postfix = "";
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rf_postfix = "";
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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@ -154,8 +155,8 @@ struct SynthNanoXplorePass : public ScriptPass
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nocy = true;
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continue;
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}
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if (args[argidx] == "-nolutram") {
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nolutram = true;
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if (args[argidx] == "-norfram") {
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norfram = true;
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continue;
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}
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if (args[argidx] == "-nobram") {
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@ -177,17 +178,20 @@ struct SynthNanoXplorePass : public ScriptPass
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if (family.empty()) {
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//log_warning("NanoXplore family not set, setting it to NG-ULTRA.\n");
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family = "ultra";
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postfix = "_u";
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}
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if (family == "ultra") {
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postfix = "_u";
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rf_postfix = "_u";
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} else if (family == "u300") {
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postfix = "_u";
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rf_postfix = "_u";
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} else if (family == "medium") {
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postfix = "_m";
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rf_postfix = "_l";
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} else if (family == "large") {
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postfix = "_l";
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rf_postfix = "_l";
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} else
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log_cmd_error("Invalid NanoXplore -family setting: '%s'.\n", family.c_str());
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@ -238,9 +242,18 @@ struct SynthNanoXplorePass : public ScriptPass
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run("opt_clean");
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}
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if (!nolutram && check_label("map_lutram", "(skip if -nolutram)")) {
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run("memory_libmap -lib +/nanoxplore/drams.txt");
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run("techmap -map +/nanoxplore/cells_map.v t:$__NX_XRFB_32x36_ t:$__NX_XRFB_64x18_");
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if (check_label("map_ram"))
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{
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std::string args = "";
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if (nobram)
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args += " -no-auto-block";
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if (norfram)
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args += " -no-auto-distributed";
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if (help_mode)
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args += " [-no-auto-block] [-no-auto-distributed]";
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run("memory_libmap -lib +/nanoxplore/rf_rams"+ rf_postfix+ ".txt -lib +/nanoxplore/brams.txt" + args, "(-no-auto-block if -nobram, -no-auto-distributed if -norfram)");
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run("techmap -map +/nanoxplore/rf_rams_map"+ rf_postfix+ ".v -map +/nanoxplore/brams_map.v");
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run("techmap -map +/nanoxplore/cells_wrap" + postfix + ".v t:NX_XRFB* t:NX_RFB*");
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}
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if (check_label("map_ffram"))
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