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Add meminit handling for NX_RFB_U

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This commit is contained in:
Miodrag Milanovic 2024-07-11 17:43:46 +02:00
parent 6876a27547
commit 1a6e5c671f
4 changed files with 120 additions and 4 deletions
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27
techlibs/nanoxplore/cells_sim_u.v
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@ -136,13 +136,38 @@ module NX_RFB_U(WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14
localparam MEM_SIZE = mode == 2 ? 64 : 32;
localparam MEM_WIDTH = mode == 3 ? 36 : 18;
localparam ADDR_WIDTH = mode == 2 ? 6 : 5;
localparam DATA_SIZE = MEM_SIZE * MEM_WIDTH;
localparam MAX_SIZE = DATA_SIZE + MEM_SIZE + 1;
reg [MEM_WIDTH-1:0] mem [MEM_SIZE-1:0];
function [DATA_SIZE-1:0] convert_initval;
input [8*MAX_SIZE-1:0] hex_initval;
reg done;
reg [DATA_SIZE-1:0] temp;
reg [7:0] char;
integer i,j;
begin
done = 1'b0;
temp = 0;
j = 0;
for (i = 0; i < MAX_SIZE; i = i + 1) begin
char = hex_initval[8*i +: 8];
if (char >= "0" && char <= "1") begin
temp[j] = char - "0";
j = j + 1;
end
end
convert_initval = temp;
end
endfunction
integer i;
reg [DATA_SIZE-1:0] mem_data;
initial begin
mem_data = convert_initval(mem_ctxt);
for (i = 0; i < MEM_SIZE; i = i + 1)
mem[i] = 36'b0;
mem[i] = mem_data[MEM_WIDTH*(MEM_SIZE-i-1) +: MEM_WIDTH];
end
wire [ADDR_WIDTH-1:0] WA = (mode==2) ? { WA6, WA5, WA4, WA3, WA2, WA1 } : { WA5, WA4, WA3, WA2, WA1 };

3
techlibs/nanoxplore/rf_rams_u.txt
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@ -25,7 +25,6 @@ ram distributed $__NX_RFB_U_DPREG_ {
widths 36 global;
}
init no_undef;
prune_rom;
port sw "W" {
clock anyedge;
@ -43,7 +42,6 @@ ram distributed $__NX_RFB_U_SPREG_ {
abits 5;
width 18;
init no_undef;
prune_rom;
port arsw "RW" {
clock anyedge;
}
@ -58,7 +56,6 @@ ram distributed $__NX_XRFB_2R_1W_ {
abits 5;
width 18;
init no_undef;
prune_rom;
port sw "W" {
clock anyedge;
}