mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 05:19:11 +00:00
Code Activity
7494 commits 124 branches 59 tags 44 MiB
Commit graph

7494 commits

This branch
This branch
All branches
Author SHA1 Message Date
Eddie Hung
43cd047fb9 Do not put constants into output_bits 2019-04-16 13:44:15 -07:00
Eddie Hung
61ca83e099 Remove write_verilog call 2019-04-16 13:24:54 -07:00
Eddie Hung
aece97024d Fix spacing 2019-04-16 13:16:20 -07:00
Eddie Hung
fc5fda595d Merge branch 'xaig' into xc7mux 2019-04-16 13:15:53 -07:00
Eddie Hung
0c8a839f13 Re-enable partsel.v test 2019-04-16 13:10:35 -07:00
Eddie Hung
afcb86c3d1 abc9 to call "setundef -zero" behaving as for abc 2019-04-16 13:10:13 -07:00
Eddie Hung
fed1f0ba63 NULL check before use 2019-04-16 12:59:48 -07:00
Eddie Hung
f22aa4422d WIP for box support 2019-04-16 12:57:27 -07:00
Eddie Hung
98c297fabf ABC to read_box before reading netlist 2019-04-16 12:44:10 -07:00
Eddie Hung
53b19ab1f5 Make cells.box whiteboxes not blackboxes 2019-04-16 12:43:14 -07:00
Eddie Hung
5189695362 read_verilog cells_box.v before techmap 2019-04-16 12:41:56 -07:00
Eddie Hung
2df7d97b72
Merge pull request #939 from YosysHQ/revert895 
Revert #895 (mux-to-shiftx optimisation)
 2019-04-16 11:59:21 -07:00
Eddie Hung
d259e6dc14 synth_xilinx: before abc read +/xilinx/cells_box.v 2019-04-16 11:21:46 -07:00
Eddie Hung
3ac4977b70 Add +/xilinx/cells_box.v containing models for ABC boxes 2019-04-16 11:21:03 -07:00
Eddie Hung
b89bb74452 For 'stat' do not count modules with abc_box_id 2019-04-16 11:19:54 -07:00
Eddie Hung
a2b106135b Do not call abc on modules with abc_box_id attr 2019-04-16 11:19:42 -07:00
Eddie Hung
8c6cf07acf Revert "Add abc_box_id attribute to MUXF7/F8 cells" 
This reverts commit 8fbbd9b129.
 2019-04-16 11:14:59 -07:00
Eddie Hung
4da4a6da2f Revert #895 2019-04-16 11:07:51 -07:00
Eddie Hung
18108e024a Use abc_box_id 2019-04-15 22:27:36 -07:00
Eddie Hung
e084240a81 Check abc_box_id attr 2019-04-15 22:25:37 -07:00
Eddie Hung
8fbbd9b129 Add abc_box_id attribute to MUXF7/F8 cells 2019-04-15 22:25:09 -07:00
Eddie Hung
538592067e Merge branch 'xaig' into xc7mux 2019-04-15 22:04:20 -07:00
Eddie Hung
0391499e46 Merge remote-tracking branch 'origin/master' into xaig 2019-04-15 21:56:45 -07:00
Eddie Hung
dca45c0888
Merge pull request #937 from YosysHQ/revert-932-eddie/fixdlatch 
Revert "Recognise default entry in case even if all cases covered (fix for #931)"
 2019-04-15 18:39:20 -07:00
Eddie Hung
b3378745fd
Revert "Recognise default entry in case even if all cases covered (fix for #931)" 2019-04-15 17:52:45 -07:00
Eddie Hung
18a4045858
Merge pull request #936 from YosysHQ/README-fix-quotes 
README: fix some incorrect quoting
 2019-04-15 12:22:05 -07:00
whitequark
6323e73cc9
README: fix some incorrect quoting. 2019-04-15 14:29:46 +00:00
Diego
f9272fc56d GoWin enablement: DRAM, initial BRAM, DRAM init, DRAM sim and synth_gowin flow 2019-04-12 23:40:02 -05:00
Eddie Hung
fecafb2207 Forgot backslashes 2019-04-12 18:22:44 -07:00
Eddie Hung
9bfcd80063 Handle __dummy_o__ and __const[01]__ in read_aiger not abc 2019-04-12 18:21:16 -07:00
Eddie Hung
482a60825b abc to ignore __dummy_o__ and __const[01]__ when re-integrating 2019-04-12 18:16:50 -07:00
Eddie Hung
fe0b421212 Output __const0__ and __const1__ CIs 2019-04-12 18:16:25 -07:00
Eddie Hung
c776db3320 Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig 2019-04-12 17:09:24 -07:00
Eddie Hung
acf3f5694b Fix inout handling for -map option 2019-04-12 17:02:24 -07:00
Eddie Hung
a16123cc7d Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig 2019-04-12 16:31:12 -07:00
Eddie Hung
d880f73c79 Merge remote-tracking branch 'origin/master' into xaig 2019-04-12 16:30:53 -07:00
Eddie Hung
88d43a519b Use -map instead of -symbols for aiger 2019-04-12 16:29:14 -07:00
Eddie Hung
686e772f0b ci_bits and co_bits now a list, order is important for ABC 2019-04-12 16:17:48 -07:00
Eddie Hung
ada130b459 Also cope with duplicated CIs 2019-04-12 16:17:12 -07:00
Eddie Hung
c748391730 WIP 2019-04-12 14:13:11 -07:00
Eddie Hung
941365b4bb Comment out 2019-04-12 12:29:04 -07:00
Eddie Hung
04e466d5e4 Add support for synth_xilinx -abc9 and ignore abc9 -dress opt 2019-04-12 12:28:37 -07:00
Eddie Hung
1c6f0cffd9 Cope with an output having same name as an input (i.e. CO) 2019-04-12 12:27:07 -07:00
Eddie Hung
f77da46a87 Merge remote-tracking branch 'origin/master' into xaig 2019-04-12 12:21:48 -07:00
Eddie Hung
db1a5ec6a2
Merge pull request #928 from litghost/add_xc7_sim_models 
Add additional cells sim models for core 7-series primitives.
 2019-04-12 11:52:45 -07:00
Eddie Hung
ca8ef92a82 PI before CI 2019-04-12 10:36:05 -07:00
Eddie Hung
8228b593ef Merge remote-tracking branch 'origin/master' into xc7mux 2019-04-12 09:46:07 -07:00
Keith Rothman
1f9235ede5 Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-04-12 09:35:15 -07:00
Clifford Wolf
9d6586b4e1
Merge pull request #933 from dh73/master 
Fixing issues in CycloneV cell sim
 2019-04-12 14:57:36 +02:00
Clifford Wolf
48bc203653
Merge pull request #932 from YosysHQ/eddie/fixdlatch 
Recognise default entry in case even if all cases covered (fix for #931)
 2019-04-12 14:57:01 +02:00