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Author	SHA1	Message	Date
Eddie Hung	cd8a640989	Reject if (* init *) present	2019-09-25 18:21:08 -07:00
Eddie Hung	34aa3532fb	Remove unnecessary check for A_SIGNED != B_SIGNED; be more explicit	2019-09-25 17:26:47 -07:00
Eddie Hung	a4238637ac	Revert "Remove _TECHMAP_CELLTYPE_ check since all $mul" ... This reverts commit 234738b103.	2019-09-25 17:25:44 -07:00
Eddie Hung	f4387e817c	Revert "No need for $__mul anymore?" ... This reverts commit 1d875ac76a.	2019-09-25 17:24:11 -07:00
Eddie Hung	aeb1539818	Rework xilinx_dsp postAdd for new wreduce call	2019-09-25 17:22:30 -07:00
Eddie Hung	63940913d2	Only wreduce on t:$add	2019-09-25 17:22:04 -07:00
Eddie Hung	234738b103	Remove _TECHMAP_CELLTYPE_ check since all $mul	2019-09-25 16:51:31 -07:00
Eddie Hung	5f8917c984	Fix memory issue since SigSpec& could be invalidated	2019-09-25 16:45:51 -07:00
Eddie Hung	1d875ac76a	No need for $__mul anymore?	2019-09-25 14:06:21 -07:00
Eddie Hung	486dd7c483	unextend only used in init	2019-09-25 14:05:59 -07:00
Eddie Hung	53ea5daa42	Call 'wreduce' after mul2dsp to avoid unextend()	2019-09-25 14:04:36 -07:00
Eddie Hung	93363c94a2	Oops. Actually use __NAME__ in ABC_DSP48E1 macro	2019-09-25 10:33:16 -07:00
Eddie Hung	b41d2fb4e4	Add (* techmap_autopurge *) to abc_unmap.v too	2019-09-23 22:02:22 -07:00
Eddie Hung	44374b1b2b	"abc_padding" attr for blackbox outputs that were padded, remove them later	2019-09-23 21:58:40 -07:00
Eddie Hung	c340fbfab2	Force $inout.out ports to begin with '$' to indicate internal	2019-09-23 21:58:04 -07:00
Eddie Hung	11ac37733d	Add techmap_autopurge to outputs in abc_map.v too	2019-09-23 21:56:28 -07:00
Eddie Hung	27167848f4	Revert "Add a xilinx_finalise pass" ... This reverts commit 23d90e0439.	2019-09-23 19:52:55 -07:00
Eddie Hung	0f53893104	Revert "Remove (* techmap_autopurge *) from abc_unmap.v since no effect" ... This reverts commit 67c2db3486.	2019-09-23 19:52:55 -07:00
Eddie Hung	29db96fa1f	Revert "Vivado does not like zero width port connections" ... This reverts commit 895e2befa7.	2019-09-23 19:52:54 -07:00
Eddie Hung	895e2befa7	Vivado does not like zero width port connections	2019-09-23 19:04:07 -07:00
Eddie Hung	67c2db3486	Remove (* techmap_autopurge *) from abc_unmap.v since no effect	2019-09-23 18:56:18 -07:00
Eddie Hung	23d90e0439	Add a xilinx_finalise pass	2019-09-23 18:56:02 -07:00
Eddie Hung	e556d48d45	Set [AB]CASCREG to legal values	2019-09-23 16:00:11 -07:00
Eddie Hung	b824a56cde	Comment to explain separating CREG packing	2019-09-23 13:58:10 -07:00
Eddie Hung	15dfbc8125	Separate out CREG packing into new pattern, to avoid conflict with PREG	2019-09-23 13:27:10 -07:00
Eddie Hung	26a6c55665	Move log_debug("\n") later	2019-09-23 13:27:00 -07:00
Eddie Hung	d0dbbc2605	Move unextend initialisation later	2019-09-23 13:26:34 -07:00
Eddie Hung	a67af3d5e5	Use new port() overload once more	2019-09-23 13:00:44 -07:00
Eddie Hung	bcee87a457	Merge remote-tracking branch 'origin/master' into xc7dsp	2019-09-23 10:58:28 -07:00
Clifford Wolf	0a2d8db793	Merge pull request #1392 from YosysHQ/eddie/fix1391 ... (* techmap_autopurge *) fixes when ports aren't consistently-sized	2019-09-21 11:25:36 +02:00
Eddie Hung	7c8de1dd18	Hell let's add the original #1381 testcase too	2019-09-20 17:58:51 -07:00
Eddie Hung	ec08a031b5	Revert abc9.cc	2019-09-20 17:52:23 -07:00
Eddie Hung	6258e6a7e2	Add testcase	2019-09-20 17:51:45 -07:00
Eddie Hung	72ce06909e	Trim mismatched connection to be same (smallest) size	2019-09-20 17:51:36 -07:00
Eddie Hung	567e5f0aa7	Fix first testcase in #1391	2019-09-20 17:51:27 -07:00
Eddie Hung	4401e5f142	Grammar	2019-09-20 14:24:31 -07:00
Eddie Hung	53817b8575	Use new port/param overload in pmg	2019-09-20 14:21:22 -07:00
Eddie Hung	d122083a11	Output pattern matcher items as log_debug()	2019-09-20 12:42:28 -07:00
Eddie Hung	95644b00cb	OPMODE is port not param	2019-09-20 12:37:29 -07:00
Eddie Hung	3fb839e255	Merge remote-tracking branch 'origin/master' into xc7dsp	2019-09-20 12:21:36 -07:00
Eddie Hung	eb597431f0	Do not run xilinx_dsp_cascadeAB for now	2019-09-20 12:18:37 -07:00
Eddie Hung	0bca366bcd	WIP for xiinx_dsp_cascadeAB	2019-09-20 12:07:14 -07:00
Eddie Hung	b0ad2592be	Run until convergence	2019-09-20 12:04:16 -07:00
Eddie Hung	1b892ca1be	Cleanup ice40_dsp.pmg	2019-09-20 12:03:45 -07:00
Eddie Hung	d88903e610	Cleanup xilinx_dsp	2019-09-20 12:03:25 -07:00
Eddie Hung	1809f463fb	More exceptions	2019-09-20 12:03:10 -07:00
Eddie Hung	ab46d9017b	Fix signedness bug	2019-09-20 10:11:36 -07:00
Eddie Hung	70c5444b25	Update doc	2019-09-20 10:07:54 -07:00
Eddie Hung	ed187ef1cf	Add a xilinx_dsp_cascade matcher for PCIN -> PCOUT	2019-09-20 10:00:09 -07:00
Eddie Hung	1844498c5f	Add an overload for port/param with default value	2019-09-20 09:59:42 -07:00