mirror of
				https://github.com/YosysHQ/yosys
				synced 2025-10-31 03:32:29 +00:00 
			
		
		
		
	ABC to read_box before reading netlist
This commit is contained in:
		
							parent
							
								
									53b19ab1f5
								
							
						
					
					
						commit
						98c297fabf
					
				
					 1 changed files with 3 additions and 1 deletions
				
			
		|  | @ -322,7 +322,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri | |||
| 	log_header(design, "Extracting gate netlist of module `%s' to `%s/input.xaig'..\n", | ||||
| 			module->name.c_str(), replace_tempdir(tempdir_name, tempdir_name, show_tempdir).c_str()); | ||||
| 
 | ||||
| 	std::string abc_script = stringf("&read %s/input.xaig; &ps ", tempdir_name.c_str()); | ||||
| 	std::string abc_script; | ||||
| 
 | ||||
| 	if (!liberty_file.empty()) { | ||||
| 		abc_script += stringf("read_lib -w %s; ", liberty_file.c_str()); | ||||
|  | @ -343,6 +343,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri | |||
| 	else | ||||
| 		abc_script += stringf("read_library %s/stdcells.genlib; ", tempdir_name.c_str()); | ||||
| 
 | ||||
| 	abc_script += stringf("&read %s/input.xaig; &ps ", tempdir_name.c_str()); | ||||
| 
 | ||||
| 	if (!script_file.empty()) { | ||||
| 		if (script_file[0] == '+') { | ||||
| 			for (size_t i = 1; i < script_file.size(); i++) | ||||
|  |  | |||
		Loading…
	
	Add table
		Add a link
		
	
		Reference in a new issue