725 commits

Author	SHA1	Message	Date
Udi Finkelstein	2dea42e903	Added $bits() for memories as well.	2017-09-26 09:11:25 +03:00
Udi Finkelstein	17f8b41605	$size() now works with memories as well!	2017-09-26 08:36:45 +03:00
Udi Finkelstein	64eb8f29ad	Add $size() function. At the moment it works only on expressions, not on memories.	2017-09-26 06:25:42 +03:00
Clifford Wolf	8f8baccfde	Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand const reg"	2017-06-07 12:30:24 +02:00
Clifford Wolf	5f1d0b1024	Add $live and $fair cell types, add support for s_eventually keyword	2017-02-25 10:36:39 +01:00
Clifford Wolf	1e927a51d5	Preserve string parameters	2017-02-23 15:39:13 +01:00
Clifford Wolf	4fb8007171	Fix incorrect "incompatible re-declaration of wire" error in tasks/functions	2017-02-14 15:10:59 +01:00
Clifford Wolf	3928482a3c	Add $cover cell type and SVA cover() support	2017-02-04 14:14:26 +01:00
Clifford Wolf	78f65f89ff	Fix bug in AstNode::mem2reg_as_needed_pass2()	2017-01-15 13:52:50 +01:00
Clifford Wolf	2d32c6c4f6	Fixed handling of local memories in functions	2017-01-05 13:19:03 +01:00
Clifford Wolf	81a9ee2360	Added handling of local memories and error for local decls in unnamed blocks	2017-01-04 16:03:04 +01:00
Clifford Wolf	dfb461fe52	Added Verilog $rtoi and $itor support	2017-01-03 17:40:58 +01:00
Clifford Wolf	70d7a02cae	Added support for hierarchical defparams	2016-11-15 13:35:19 +01:00
Clifford Wolf	a926a6afc2	Remember global declarations and defines accross read_verilog calls	2016-11-15 12:42:43 +01:00
Clifford Wolf	2874914bcb	Fixed anonymous genblock object names	2016-11-04 07:46:30 +01:00
Clifford Wolf	56e2bb88ae	Some fixes in handling of signed arrays	2016-11-01 23:17:43 +01:00
Clifford Wolf	aa72262330	Added avail params to ilang format, check module params in 'hierarchy -check'	2016-10-22 11:05:49 +02:00
Clifford Wolf	bdc316db50	Added $anyseq cell type	2016-10-14 15:24:03 +02:00
Clifford Wolf	53655d173b	Added $global_clock verilog syntax support for creating $ff cells	2016-10-14 12:33:56 +02:00
Clifford Wolf	aaa99c35bd	Added $past, $stable, $rose, $fell SVA functions	2016-09-19 01:30:07 +02:00
Clifford Wolf	ab18e9df7c	Added assertpmux	2016-09-07 00:28:01 +02:00
Clifford Wolf	97583ab729	Avoid creation of bogus initial blocks for assert/assume in always @*	2016-09-06 17:34:42 +02:00
Clifford Wolf	aa25a4cec6	Added $anyconst support to yosys-smtbmc	2016-08-30 19:27:42 +02:00
Clifford Wolf	6f41e5277d	Removed $aconst cell type	2016-08-30 19:09:56 +02:00
Clifford Wolf	eae390ae17	Removed $predict again	2016-08-28 21:35:33 +02:00
Clifford Wolf	450f6f59b4	Fixed bug with memories that do not have a down-to-zero data width	2016-08-22 14:27:46 +02:00
Clifford Wolf	82a4a0230f	Another bugfix in mem2reg code	2016-08-21 13:23:58 +02:00
Clifford Wolf	dbdd8927e7	Minor improvements to AstNode::dumpAst() and AstNode::dumpVlog()	2016-08-21 13:18:09 +02:00
Clifford Wolf	fe9315b7a1	Fixed finish_addr handling in $readmemh/$readmemb	2016-08-20 13:47:46 +02:00
Clifford Wolf	f6629b9c29	Optimize memory address port width in wreduce and memory_collect, not verilog front-end	2016-08-19 18:38:25 +02:00
Clifford Wolf	e9fe57c75e	Only allow posedge/negedge with 1 bit wide signals	2016-08-10 19:32:11 +02:00
Clifford Wolf	4056312987	Added $anyconst and $aconst	2016-07-27 15:41:22 +02:00
Clifford Wolf	a7b0769623	Added "read_verilog -dump_rtlil"	2016-07-27 15:40:17 +02:00
Clifford Wolf	7fef5ff104	Using $initstate in "initial assume" and "initial assert"	2016-07-21 14:37:28 +02:00
Clifford Wolf	5c166e76e5	Added $initstate cell type and vlog function	2016-07-21 14:23:22 +02:00
Clifford Wolf	d7763634b6	After reading the SV spec, using non-standard predict() instead of expect()	2016-07-21 13:34:33 +02:00
Clifford Wolf	721f1f5ecf	Added basic support for $expect cells	2016-07-13 16:56:17 +02:00
Clifford Wolf	9a101dc1f7	Fixed mem assignment in left-hand-side concatenation	2016-07-08 14:31:06 +02:00
Ruben Undheim	a8200a773f	A few modifications after pull request comments ... - Renamed Design::packages to Design::verilog_packages - No need to include ast.h in rtlil.h	2016-06-18 14:23:38 +02:00
Ruben Undheim	178ff3e7f6	Added support for SystemVerilog packages with localparam definitions	2016-06-18 10:53:55 +02:00
Clifford Wolf	766032c5f8	Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}	2016-05-27 17:55:03 +02:00
Clifford Wolf	ee071586c5	Fixed access-after-delete bug in mem2reg code	2016-05-27 17:25:33 +02:00
Clifford Wolf	e9ceec26ff	fixed typos in error messages	2016-05-27 16:37:36 +02:00
Clifford Wolf	570014800a	Include <cmath> in yosys.h	2016-05-08 10:50:39 +02:00
Clifford Wolf	0bc95f1e04	Added "yosys -D" feature	2016-04-21 23:28:37 +02:00
Clifford Wolf	5a09fa4553	Fixed handling of parameters and const functions in casex/casez pattern	2016-04-21 15:31:54 +02:00
Clifford Wolf	5328a85149	Do not set "nosync" on task outputs, fixes #134	2016-03-24 12:16:47 +01:00
Clifford Wolf	4f0d4899ce	Added support for $stop system task	2016-03-21 16:19:51 +01:00
Clifford Wolf	e5d42ebb4d	Added $display %m support, fixed mem leak in $display, fixes #128	2016-03-19 11:51:13 +01:00
Clifford Wolf	ef4207d5ad	Fixed localparam signdness, fixes #127	2016-03-18 12:15:00 +01:00