mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-30 04:15:52 +00:00
Code Activity
4807 commits 102 branches 53 tags 49 MiB
Commit graph

4807 commits

This branch
This branch
All branches
Author SHA1 Message Date
Eddie Hung
c997a77014 Ignore 'whitebox' attr in flatten with "-wb" option 2019-04-18 10:19:45 -07:00
Eddie Hung
9278192efe Also update Makefile.inc 2019-04-18 09:58:34 -07:00
Eddie Hung
7b6ab937c1 Make SB_LUT4 a blackbox 2019-04-18 09:05:22 -07:00
Eddie Hung
8024f41897 Fix rename 2019-04-18 09:04:34 -07:00
Eddie Hung
ed5e75ed7d Rename to abc_*.{box,lut} 2019-04-18 09:02:58 -07:00
Eddie Hung
8fe0a961b3 Merge remote-tracking branch 'origin/clifford/whitebox' into xaig 2019-04-18 09:00:06 -07:00
Clifford Wolf
f4abc21d8a Add "whitebox" attribute, add "read_verilog -wb" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-18 17:45:47 +02:00
Eddie Hung
a20ed260e1 Skip if abc_box_id earlier 2019-04-17 16:36:03 -07:00
Eddie Hung
709f76c107 Remove use of abc_box_id in stat 2019-04-17 16:35:27 -07:00
Eddie Hung
23cd2e5de0 Fix $anyseq warning and cleanup 2019-04-17 16:03:29 -07:00
Eddie Hung
8fd455c910 Update Makefile.inc too 2019-04-17 15:19:48 -07:00
Eddie Hung
c795e14d25 Reduce to three devices: hx, lp, u 2019-04-17 15:19:02 -07:00
Eddie Hung
abcd3103ff Do not print slack histogram 2019-04-17 15:11:14 -07:00
Eddie Hung
5c0853fc51 Add up5k timings 2019-04-17 15:10:39 -07:00
Eddie Hung
4b520ae627 Fix grammar 2019-04-17 15:10:22 -07:00
Eddie Hung
3105a8a653 Update error message 2019-04-17 15:07:44 -07:00
Eddie Hung
6f3e5297db Add "-device" argument to synth_ice40 2019-04-17 15:04:46 -07:00
Eddie Hung
671cca59a9 Missing abc_flop_q attribute on SPRAM 2019-04-17 14:44:08 -07:00
Eddie Hung
1ec5f18346 Cope with inout ports 2019-04-17 14:43:45 -07:00
Eddie Hung
437fec0d88 Map to SB_LUT4 from fastest input first 2019-04-17 13:01:17 -07:00
Eddie Hung
fd89c1056e Working ABC9 script 2019-04-17 12:33:32 -07:00
Eddie Hung
2b860809e9 Stop topological sort at abc_flop_q 2019-04-17 12:28:19 -07:00
Eddie Hung
58847df1b9 Mark seq output ports with "abc_flop_q" attr 2019-04-17 12:27:45 -07:00
Eddie Hung
1eade06671 Also update Makefile.inc 2019-04-17 12:27:02 -07:00
Eddie Hung
4fb9ccfcd8 synth_ice40 to use renamed files 2019-04-17 12:22:03 -07:00
Eddie Hung
42c33db22c Rename to abc.* 2019-04-17 12:15:34 -07:00
Eddie Hung
c1ebe51a75 Revert "Try using an ICE40_CARRY_LUT primitive to avoid ABC issues" 
This reverts commit a7632ab332.
 2019-04-17 11:10:20 -07:00
Eddie Hung
a7632ab332 Try using an ICE40_CARRY_LUT primitive to avoid ABC issues 2019-04-17 11:10:04 -07:00
Eddie Hung
d59185f1d6 Remove init* from xaiger, also topo-sort cells for box flow 2019-04-17 11:08:42 -07:00
Eddie Hung
116176e151 Merge remote-tracking branch 'origin/master' into xaig 2019-04-17 11:01:15 -07:00
Eddie Hung
e1b550d203 Ignore a/i/o/h XAIGER extensions 2019-04-17 10:55:23 -07:00
Eddie Hung
17fb6c3522 Fix spacing 2019-04-17 08:40:50 -07:00
Clifford Wolf
ea8ac0aaad Update to ABC d1b6413 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-17 13:51:34 +02:00
Eddie Hung
5c134980c4 Optimise 2019-04-16 21:05:44 -07:00
Eddie Hung
743c164eee Add SB_LUT4 to box library 2019-04-16 17:34:11 -07:00
Eddie Hung
7980118d74 Add ice40 box files 2019-04-16 16:39:30 -07:00
Eddie Hung
ae2653c50f abc9 to output some more info 2019-04-16 16:39:16 -07:00
Eddie Hung
e7a8955818 CIs before PIs; also sort each cell's connections before iterating 2019-04-16 16:37:47 -07:00
Eddie Hung
b015ed48f7 Merge remote-tracking branch 'origin/master' into xaig 2019-04-16 15:04:20 -07:00
Eddie Hung
55a3638c71 Port from xc7mux branch 2019-04-16 15:01:45 -07:00
Eddie Hung
0c8a839f13 Re-enable partsel.v test 2019-04-16 13:10:35 -07:00
Eddie Hung
afcb86c3d1 abc9 to call "setundef -zero" behaving as for abc 2019-04-16 13:10:13 -07:00
Eddie Hung
2df7d97b72
Merge pull request #939 from YosysHQ/revert895 
Revert #895 (mux-to-shiftx optimisation)
 2019-04-16 11:59:21 -07:00
Eddie Hung
4da4a6da2f Revert #895 2019-04-16 11:07:51 -07:00
Eddie Hung
0391499e46 Merge remote-tracking branch 'origin/master' into xaig 2019-04-15 21:56:45 -07:00
Eddie Hung
dca45c0888
Merge pull request #937 from YosysHQ/revert-932-eddie/fixdlatch 
Revert "Recognise default entry in case even if all cases covered (fix for #931)"
 2019-04-15 18:39:20 -07:00
Eddie Hung
b3378745fd
Revert "Recognise default entry in case even if all cases covered (fix for #931)" 2019-04-15 17:52:45 -07:00
Eddie Hung
18a4045858
Merge pull request #936 from YosysHQ/README-fix-quotes 
README: fix some incorrect quoting
 2019-04-15 12:22:05 -07:00
whitequark
6323e73cc9
README: fix some incorrect quoting. 2019-04-15 14:29:46 +00:00
Eddie Hung
fecafb2207 Forgot backslashes 2019-04-12 18:22:44 -07:00