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Code Activity
14685 commits 122 branches 59 tags 72 MiB
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Author SHA1 Message Date
Roland Coeurjoly
5fca9b867d Add Get vcd2fst step to test-yosys job 
Co-authored-by: Miodrag Milanovic <mmicko@gmail.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
 2024-09-30 16:25:32 +02:00
Akash Levy
e21d007791 Bump dep version 2024-09-30 02:54:46 -07:00
Akash Levy
ee0b083a1e
Merge branch 'YosysHQ:main' into main 2024-09-30 02:43:09 -07:00
github-actions[bot]
59404f8ce5 Bump version 2024-09-30 00:21:26 +00:00
rherveille
ce7db661a8
Added cast to type support (#4284) 2024-09-29 17:03:01 -04:00
Akash Levy
599cebfca5 Include pmuxtree 2024-09-29 05:31:51 -07:00
Akash Levy
49d948d873 Fix splitfanout: keep original cell, add new cells to driver db to fix net messup 2024-09-29 03:07:07 -07:00
Akash Levy
9ecb4e798e Update deps 2024-09-28 19:49:07 -07:00
Akash Levy
0610d6ccc2 Smallfix to get GHDL working 2024-09-27 06:38:42 -07:00
Akash Levy
bb2cdd61fe Fix GHDL and bump yosys-slang 2024-09-27 04:43:59 -07:00
Akash Levy
5a27db1463 Smallfix 2024-09-27 03:31:30 -07:00
Akash Levy
f6d577aed1 Fix GHDL support 2024-09-27 03:14:15 -07:00
Akash Levy
9f4d385e35 Update yosys-slang 2024-09-27 03:06:10 -07:00
Akash Levy
7f05f0b273 Fix muxadd peepopt to track bitsplit 2024-09-27 02:28:32 -07:00
Akash Levy
b1383a80cf Make renaming nicer for bmuxmap -pmux 2024-09-27 00:54:05 -07:00
Akash Levy
dbaaf78044 Iterate to new wire 2024-09-24 16:47:35 -07:00
Akash Levy
ebf8783b4b Fixup parameters 2024-09-24 13:55:09 -07:00
Martin Povišer
3e3515e7d9 log: Never silence log_cmd_error 
Add extra handling to arrange for `log_cmd_error` never being silenced
by the command line `-v N` option. Similar path for `log_error` exists
already.
 2024-09-24 17:47:46 +02:00
George Rennie
b788de9329 smtbmc: escape path identifiers 
* also changes the print format for cover statements to be more uniform
  with the asserts, allowing easier parsing of cover path
* this allows diambiguation of properties with the same name but
  different paths (see https://github.com/YosysHQ/sby/issues/296)
 2024-09-24 03:01:49 +01:00
Akash Levy
08fe6f66aa Fix functional 2024-09-23 06:56:12 -07:00
Akash Levy
a5c115f333 Update yosys-slang dep 2024-09-23 06:28:46 -07:00
Akash Levy
9193b0e324
Merge branch 'YosysHQ:main' into main 2024-09-23 06:27:58 -07:00
N. Engelhardt
8e1e2b9a39
Merge pull request #4495 from povik/check-avert-costly-detail 2024-09-23 15:19:48 +02:00
Akash Levy
ed2c65314b Standardize convention, add back test, update README 2024-09-23 06:06:43 -07:00
Akash Levy
9e9d4359d4 Smallfix 2024-09-23 05:57:09 -07:00
Akash Levy
6b9c45a841 Enable only the test suites we need 2024-09-23 05:39:56 -07:00
Akash Levy
db14842d9c Skip some various tests and fix scopeinfo to match our convention 2024-09-23 05:39:39 -07:00
Akash Levy
138228d96e Update Verific README 2024-09-23 05:35:48 -07:00
Akash Levy
fb32031273 Skip combo loop test and mark wreduce as failing (FIXME) 2024-09-23 05:35:27 -07:00
Akash Levy
79a14e2072 Skip opt_lut test 2024-09-23 05:35:03 -07:00
Akash Levy
a4bc124e3b Add abc back for testing 2024-09-23 05:30:40 -07:00
Akash Levy
0fd6e29e8e Fixups 2024-09-23 04:25:10 -07:00
Akash Levy
0b8d951493 Add synopsys VHDL libs by default in GHDL 2024-09-23 04:05:27 -07:00
Akash Levy
2d771a352e Clean up Verific tests 2024-09-23 04:05:08 -07:00
Akash Levy
2c3d2b3ec6 Clocking works with -formal flag 2024-09-22 08:01:16 -07:00
Akash Levy
69bf7875dd Small edits 2024-09-22 07:52:58 -07:00
Akash Levy
d655766c49 Smallfix 2024-09-22 06:57:28 -07:00
Akash Levy
89f9035a98 Fix VHDL checking 2024-09-22 06:45:47 -07:00
Akash Levy
7d5dac7255 More apt location for whereami 2024-09-22 06:02:20 -07:00
Akash Levy
f1ab51ce5b Clean up and remove hdl_file_sort 2024-09-22 05:58:17 -07:00
Akash Levy
facb9e8abe Disable plugins and slang for now 2024-09-22 05:24:23 -07:00
Akash Levy
f0b1d2cac5 Small changes 2024-09-22 01:11:26 -07:00
Akash Levy
3b8c607dfd Update yosys-slang 2024-09-21 22:18:50 -07:00
Akash Levy
7f38ea8721 Update yosys-slang 2024-09-19 16:43:01 -07:00
Akash Levy
494eba8d66 Update yosys-slang 2024-09-19 16:36:30 -07:00
Martin Povišer
9018d06a33 quicklogic: Avoid carry chains in division mapping 
The default mapping rules for division-like operations (div/divfloor/
mod/modfloor) invoke subtractions which can get mapped to carry chains
in FPGA flows. Optimizations across carry chains are weak, so in
practice this ends up too costly compared to implementing the division
purely in soft logic.

For this reason arrange for `techmap.v` ignoring division operations
under `-D NODIV`, and use this mode in `synth_quicklogic` to avoid carry
chains for divisions.
 2024-09-19 12:18:47 +02:00
Akash Levy
4cf9bb86ca Smallfix 2024-09-19 01:04:29 -07:00
Akash Levy
7988a61f8c Use enable debug and switch order of Verific opt passes 2024-09-19 00:48:31 -07:00
Akash Levy
03f740e2a4 Undo annoying commit bdc43c6592 2024-09-18 22:05:23 -07:00
Akash Levy
db0317afc5 Add support for int stuff 2024-09-18 16:46:53 -07:00