3256 commits

This branch

This branch

All branches

Author	SHA1	Message	Date
Clifford Wolf	c855353986	Improve smt2 encodings of assert/assume/cover, better wire_smt2 help msg	2017-03-04 23:41:54 +01:00
Clifford Wolf	a6ca28276e	Add write_aiger $anyseq support	2017-03-02 16:39:48 +01:00
Clifford Wolf	5b3b5ffc8c	Allow $anyconst, etc. in non-formal SV mode	2017-03-01 10:47:05 +01:00
Clifford Wolf	180d704568	Disable opt_merge for $anyseq and $anyconst	2017-02-28 22:17:00 +01:00
Clifford Wolf	fbd52ec6dd	Use hex addresses in smtbmc vcd mem traces	2017-02-28 13:54:50 +01:00
Clifford Wolf	1a6c02a532	Add "chformal -assert2assume" and friends	2017-02-28 00:00:44 +01:00
Clifford Wolf	db7fc0e32d	Add "chformal" pass	2017-02-27 13:25:28 +01:00
Clifford Wolf	2203562268	Add smtbmc support for memory vcd dumping	2017-02-26 21:26:32 +01:00
Clifford Wolf	80ecd7a26f	Fix extra newline bug in write_smt2	2017-02-26 14:41:27 +01:00
Clifford Wolf	6e152f7aa1	Fix bug in smtio unroll code	2017-02-26 14:39:07 +01:00
Clifford Wolf	66a1617b69	Fix assert checking in "yosys-smtbmc -c --append"	2017-02-26 11:06:26 +01:00
Clifford Wolf	fd1cc0c73d	Improve (and fix for stbv mode) SMT2 memory API	2017-02-26 10:58:34 +01:00
Clifford Wolf	38bf458037	Add support for "yosys-smtbmc -c --append"	2017-02-25 23:41:40 +01:00
Clifford Wolf	d6858ad15b	Update ABC to hg rev 3a95bfa55df7	2017-02-25 22:59:34 +01:00
Clifford Wolf	eec2df6ad1	Merge branch 'klammerj-master'	2017-02-25 16:36:23 +01:00
Clifford Wolf	c7d1286728	Improve "write_edif" help message	2017-02-25 16:35:53 +01:00
Clifford Wolf	dfddf391f9	Move EdifNames out of double-private namespace	2017-02-25 16:29:27 +01:00
Clifford Wolf	8c61ecdd6e	Clean up edif code, swap bit indexing of "upto" ports	2017-02-25 16:28:34 +01:00
Clifford Wolf	b76c89a5dd	Merge branch 'master' of https://github.com/klammerj/yosys into klammerj-master	2017-02-25 15:59:02 +01:00
Clifford Wolf	f3324ed0cc	Merge branch 'master' of github.com:cliffordwolf/yosys	2017-02-25 13:08:27 +01:00
Clifford Wolf	dac0842d61	Add $live and $fair support to AIGER back-end.	2017-02-25 13:07:15 +01:00
Clifford Wolf	5f1d0b1024	Add $live and $fair cell types, add support for s_eventually keyword	2017-02-25 10:36:39 +01:00
Clifford Wolf	931d775b0b	Merge pull request #322 from azonenberg/master ... Add POUT to GP_COUNTx cells	2017-02-24 19:23:29 +01:00
Clifford Wolf	7af9727f78	Add "write_smt2 -stbv"	2017-02-24 18:24:53 +01:00
Andrew Zonenberg	1f824fa643	Merge https://github.com/cliffordwolf/yosys	2017-02-24 08:12:45 -08:00
Clifford Wolf	a9c3acf5a2	Add SMT2 statebv mode (inactive for now)	2017-02-24 14:04:52 +01:00
Johann Klammer	6d7a77dbf6	Did as you requested, /but/... ... Now the nets are wired in reverse again because the netlister still uses zero-based indices.	2017-02-24 13:18:49 +01:00
Clifford Wolf	f648b7cf79	Merge pull request #320 from joshhead/uninstall-binpath-fix ... Add missing slashes in paths for make uninstall	2017-02-24 12:48:12 +01:00
Josh Headapohl	fde9fdfbe8	Add missing slashes in paths for make uninstall ... Running make uninstall used to fail to remove binaries: rm -vf /usr/local/binyosys /usr/local/binyosys-config #...etc Fix Makefile so that it runs a command like this: rm -vf /usr/local/bin/yosys /usr/local/bin/yosys-config #...etc	2017-02-23 20:21:03 -05:00
Johann Klammer	06df86aae3	add options for edif flavors ... *to force renames on wide ports *to choose array delimiters *to choose up or downwards indices	2017-02-23 19:42:37 +01:00
Clifford Wolf	00dba4c197	Add support for SystemVerilog unique, unique0, and priority case	2017-02-23 16:33:19 +01:00
Clifford Wolf	1e927a51d5	Preserve string parameters	2017-02-23 15:39:13 +01:00
Clifford Wolf	c6d8d70109	Fix mingw compile issue (2nd attempt)	2017-02-23 14:21:02 +01:00
Clifford Wolf	0822b21844	Fix mingw compile issue (maybe.. I can't test it)	2017-02-23 13:59:02 +01:00
Clifford Wolf	34d4e72132	Added SystemVerilog support for ++ and --	2017-02-23 11:21:33 +01:00
Clifford Wolf	d25b6a72ee	Update ABC to hg rev 8da4dc435b9f	2017-02-22 19:20:47 +01:00
Clifford Wolf	242c5f01de	Add "yosys-smtbmc -S <opt>"	2017-02-19 22:51:29 +01:00
Andrew Zonenberg	2eabe43efa	Merge https://github.com/cliffordwolf/yosys	2017-02-16 07:48:44 -08:00
Clifford Wolf	cf25dc9ce7	Copy attributes to _TECHMAP_REPLACE_ cells	2017-02-16 12:28:42 +01:00
Clifford Wolf	e6d56d23b5	Fix eval implementation of $_NOR_	2017-02-16 12:17:03 +01:00
Andrew Zonenberg	6fed2dc996	Merge https://github.com/cliffordwolf/yosys	2017-02-14 08:29:37 -08:00
Clifford Wolf	4fb8007171	Fix incorrect "incompatible re-declaration of wire" error in tasks/functions	2017-02-14 15:10:59 +01:00
Clifford Wolf	4e80ce97a8	Add warning about x/z bits left unconnected in EDIF output	2017-02-14 12:49:35 +01:00
Clifford Wolf	2a311c2c38	Fix double-call of log_pop() in synth_greenpak4	2017-02-14 11:57:54 +01:00
Clifford Wolf	f3a25d9d34	Merge pull request #313 from azidar/bugfix-assign-wmask ... More progress on Firrtl backend.	2017-02-14 11:49:14 +01:00
Adam Izraelevitz	794cec0016	More progress on Firrtl backend. ... Chisel -> Firrtl -> Verilog -> Firrtl -> Verilog is successful for a simple rocket-chip design.	2017-02-13 11:17:53 -08:00
Clifford Wolf	69468d5a16	Do not fix port widths on any blackbox instances	2017-02-13 17:07:38 +01:00
Clifford Wolf	db7314bc02	Fix techmap for inout ports connected to inout ports	2017-02-13 16:55:25 +01:00
Clifford Wolf	76c4ee096b	Do not eagerly fix port widths on parameterized cells	2017-02-12 17:42:57 +01:00
Clifford Wolf	828303791b	Add "yosys -w" for suppressing warnings	2017-02-12 11:11:00 +01:00