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7901 commits 122 branches 59 tags 72 MiB
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Author SHA1 Message Date
Eddie Hung
c761fa49b7 Missing endmodule 2019-11-22 12:37:57 -08:00
Eddie Hung
0ab1e496dc write_xaiger to not use module POs but only write outputs if driven 2019-11-21 16:19:28 -08:00
Eddie Hung
c4ec42ac38 When expanding upwards, do not capture $__ABC9_{FF,ASYNC}_ 
Since they should be captured downwards from the owning flop
 2019-11-21 16:17:03 -08:00
Eddie Hung
5a30e3ac3b Merge branch 'eddie/xaig_dff_adff' into xaig_dff 2019-11-21 16:15:25 -08:00
Eddie Hung
911a152b39 Add test 2019-11-21 16:13:28 -08:00
Eddie Hung
a576747483 Consistent log message, ignore 's' extension 2019-11-20 15:40:46 -08:00
Eddie Hung
729c6b93e8 endomain -> ctrldomain 2019-11-20 14:32:01 -08:00
Eddie Hung
af3055fe83 Add blackbox model for $__ABC9_FF_ so that clock partitioning works 2019-11-20 14:30:56 -08:00
Eddie Hung
cd9e830b67 Add multi clock test 2019-11-20 13:28:55 -08:00
Eddie Hung
df63d75ff3 Fix INIT values 2019-11-20 11:26:59 -08:00
Eddie Hung
1cc106452f Add a equiv test too 2019-11-19 17:05:14 -08:00
Eddie Hung
90c5ca330c Add two tests 2019-11-19 16:57:58 -08:00
Eddie Hung
929beda19c abc9 to support async flops $_DFF_[NP][NP][01]_ 2019-11-19 16:57:26 -08:00
Eddie Hung
344619079d Do not drop async control signals in abc_map.v 2019-11-19 16:57:07 -08:00
Eddie Hung
09ee96e8c2 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-11-19 15:40:39 -08:00
Clifford Wolf
7ea0a5937b
Merge pull request #1449 from pepijndevos/gowin 
Improvements for gowin support
 2019-11-19 17:29:27 +01:00
Pepijn de Vos
8ab412eb16 Remove dff init altogether 
The hardware does not actually support it.
In reality it is always initialised to its reset value.
 2019-11-19 15:53:44 +01:00
Marcin Kościelnicki
15232a48af Fix #1462, #1480. 2019-11-19 08:57:39 +01:00
Marcin Kościelnicki
7a9081440c xilinx: Add simulation models for MULT18X18* and DSP48A*. 
This adds simulation models for the following primitives:

- MULT18X18 and MULT18X18S (Virtex 2*, Spartan 3)
- MULT18X18SIO (Spartan 3E, Spartan 3A)
- DSP48A (Spartan 3A DSP) — implemented in terms of DSP48A1
- DSP48A1 (Spartan 6)
 2019-11-19 01:00:58 +01:00
Pepijn de Vos
dd8c7e1ddd add help for nowidelut and abc9 options 2019-11-18 14:26:09 +01:00
Clifford Wolf
9ee3c57e46
Merge pull request #1497 from YosysHQ/mwk/extract-fa-fix 
Fix #1496.
 2019-11-18 10:53:14 +01:00
whitequark
cdb566b2d6
Merge pull request #1494 from whitequark/write_verilog-extmem 
write_verilog: add -extmem option, to write split memory init files
 2019-11-18 09:37:14 +00:00
Marcin Kościelnicki
38e72d6e13 Fix #1496. 2019-11-18 04:16:48 +01:00
whitequark
3c643c57df write_verilog: add -extmem option, to write split memory init files. 
Some toolchains (in particular Quartus) are pathologically slow if
a large amount of assignments in `initial` blocks are used.
 2019-11-18 01:27:21 +00:00
Clifford Wolf
527434de49
Merge pull request #1492 from YosysHQ/dave/wreduce-fix-arst 
wreduce: Don't trim zeros or sext when not matching ARST_VALUE
 2019-11-17 10:42:30 +01:00
Pepijn de Vos
32f0296df1 Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin 2019-11-16 12:43:17 +01:00
David Shah
51e4e29bb1 ecp5: Use new autoname pass for better cell/net names 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-15 21:03:11 +00:00
David Shah
f5804a84fd wreduce: Don't trim zeros or sext when not matching ARST_VALUE 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-14 18:43:15 +00:00
Clifford Wolf
e907ee4fde
Merge pull request #1490 from YosysHQ/clifford/autoname 
Add "autoname" pass and use it in "synth_ice40"
 2019-11-14 18:03:44 +01:00
Clifford Wolf
4b18a4528b
Merge pull request #1444 from btut/feature/python_wrappers/globals_and_streams 
Python Wrappers: Expose global variables and allow logging to python streams
 2019-11-14 12:10:12 +01:00
Clifford Wolf
056ef76711
Merge pull request #1465 from YosysHQ/dave/ice40_timing_sim 
ice40: Support for post-place-and-route timing simulations
 2019-11-14 12:07:25 +01:00
Clifford Wolf
f453f579bf Merge branch 'makaimann-label-bads-btor' 2019-11-14 11:57:53 +01:00
Clifford Wolf
cd44826d50 Use cell name for btor bad state props when it is a public name 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-11-14 11:57:38 +01:00
Clifford Wolf
89834b98f7 Merge branch 'label-bads-btor' of https://github.com/makaimann/yosys into makaimann-label-bads-btor 2019-11-14 11:52:41 +01:00
Clifford Wolf
07c854b7af Add "autoname" pass and use it in "synth_ice40" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-11-13 13:41:16 +01:00
whitequark
ab0fb19cff
Merge pull request #1488 from whitequark/flowmap-fixes 
flowmap: fix a few crashes
 2019-11-13 11:57:17 +00:00
Clifford Wolf
6e332161db
Merge pull request #1486 from YosysHQ/clifford/fsmdetectfix 
Bugfix in fsm_detect
 2019-11-13 12:34:27 +01:00
Clifford Wolf
4be5a0fd7c Update fsm_detect bugfix 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-11-12 17:31:30 +01:00
Clifford Wolf
16df8f5a32 Bugfix in fsm_detect 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-11-12 14:26:02 +01:00
Clifford Wolf
e0ba78bdf2
Merge pull request #1484 from YosysHQ/clifford/cmp2luteqne 
Do not map $eq and $ne in cmp2lut, only proper arithmetic cmp
 2019-11-12 10:24:12 +01:00
Makai Mann
d88cc139a0 Add an info string symbol for bad states in btor backend 2019-11-11 16:40:51 -08:00
whitequark
c68722818a flowmap: when doing mincut, ensure source is always in X, not X̅. 
Fixes #1475.
 2019-11-12 00:15:43 +00:00
whitequark
eef32195bd flowmap: don't break if that creates a k+2 (and larger) LUT either. 
Fixes #1405.
 2019-11-11 23:13:00 +00:00
Pepijn de Vos
ab8c521030 fix fsm test with proper clock enable polarity 2019-11-11 17:51:26 +01:00
Pepijn de Vos
ec3faa7b96 Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin 2019-11-11 17:08:40 +01:00
Miodrag Milanovic
3e0ffe05a7 Fixed tests 2019-11-11 15:41:33 +01:00
Clifford Wolf
362f4f996d Do not map $eq and $ne in cmp2lut, only proper arithmetic cmp 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-11-11 15:07:29 +01:00
Clifford Wolf
1d148491c5
Merge pull request #1470 from YosysHQ/clifford/subpassdoc 
Add CodingReadme section on script passes
 2019-11-10 11:00:38 +01:00
Clifford Wolf
65f197e28f Add check for valid macro names in macro definitions 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-11-07 13:30:03 +01:00
Pepijn de Vos
0e5dbc4abc fix wide luts 2019-11-06 19:48:18 +01:00