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Author SHA1 Message Date
whitequark
c55dfb8369 opt_lut: reflect changes in sigmap. 
Otherwise, some LUTs will be missed during elimination.
 2019-01-02 10:21:58 +00:00
whitequark
06143ab33f opt_lut: use a worklist, and revisit cells affected by elimination. 2019-01-02 09:36:32 +00:00
whitequark
f7363ac508 opt_lut: count eliminated cells, and set opt.did_something for them. 2019-01-02 09:14:43 +00:00
Clifford Wolf
4b9f619349
Merge pull request #768 from whitequark/opt_lut_elim 
opt_lut: eliminate LUTs evaluating to constants or inputs
 2019-01-01 11:13:48 +01:00
whitequark
42c356c49c opt_lut: eliminate LUTs evaluating to constants or inputs. 2018-12-31 23:55:40 +00:00
Clifford Wolf
0a840dd883 Fix handling of (* keep *) wires in wreduce 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-31 16:37:40 +01:00
Clifford Wolf
e09e49ca54
Merge pull request #766 from Icenowy/anlogic-latches 
anlogic: add latch cells
 2018-12-31 15:52:01 +01:00
Larry Doolittle
ebe9351f82 Fix 7 instances of add_share_file to add_gen_share_file 
in techlibs/ecp5/Makefile.inc to permit out-of-tree builds
 2018-12-29 12:53:12 +01:00
Larry Doolittle
99706b3bf4 Squelch a little more trailing whitespace 2018-12-29 12:46:54 +01:00
Icenowy Zheng
1b36944299 anlogic: add latch cells 
Add latch cells to Anlogic cells replacement library by copying other
FPGAs' latch code to it.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
 2018-12-25 22:47:46 +08:00
Clifford Wolf
245724a504
Merge pull request #761 from whitequark/proc_clean_partial 
proc_clean: remove any empty cases, if possible to do safely
 2018-12-23 16:16:06 +01:00
Clifford Wolf
6dad191377 Add "read_ilang -[no]overwrite" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-23 15:45:09 +01:00
Clifford Wolf
d938ce7ab6 Merge branch 'master' of github.com:YosysHQ/yosys 2018-12-23 15:44:19 +01:00
whitequark
18291c20d2 proc_clean: remove any empty cases if all cases use all-def compare. 2018-12-23 09:04:30 +00:00
Clifford Wolf
e5eb3d2c8a
Merge pull request #757 from whitequark/manual_mem 
manual: document $meminit cell and memory_* passes
 2018-12-22 20:12:18 +01:00
whitequark
b784440857 proc_clean: remove any empty cases at the end of the switch. 
Previously, only completely empty switches were removed.
 2018-12-22 09:04:46 +00:00
whitequark
182d84ad54 manual: make description of $meminit ports match reality. 2018-12-21 23:04:31 +00:00
Clifford Wolf
ee8a7589e0
Merge pull request #758 from whitequark/tcl_script_args 
tcl: add support for passing arguments to scripts
 2018-12-21 17:56:43 +01:00
Clifford Wolf
29a82acb2e
Merge pull request #759 from whitequark/memory_collect_init_x 
memory_collect: do not truncate 'x from \INIT
 2018-12-21 17:39:52 +01:00
whitequark
0c318e7db5 memory_collect: do not truncate 'x from \INIT. 
The semantics of an RTLIL constant that has less bits than its
declared bit width is zero padding. Therefore, if the output of
memory_collect will be used for simulation, truncating 'x from
the end of \INIT will produce incorrect simulation results.
 2018-12-21 02:01:27 +00:00
whitequark
c04908c997 manual: fix typos. 2018-12-20 07:59:40 +00:00
whitequark
2ca237e086 tcl: add support for passing arguments to scripts. 2018-12-20 07:32:24 +00:00
whitequark
a9ff81dd82 manual: document $meminit cell and memory_* passes. 2018-12-20 04:54:31 +00:00
Clifford Wolf
93d44bb9a6
Merge pull request #752 from Icenowy/anlogic-lut-cost 
Anlogic: let LUT5/6 have more cost than LUT4-
 2018-12-19 19:52:31 +01:00
Clifford Wolf
c98d44ac12
Merge pull request #753 from Icenowy/anlogic-makefile-fix 
anlogic: fix Makefile.inc
 2018-12-19 19:51:10 +01:00
Clifford Wolf
4d84a456dc
Merge pull request #749 from Icenowy/anlogic-dram-fix 
anlogic: fix dbits of Anlogic Eagle DRAM16X4
 2018-12-19 19:48:54 +01:00
Icenowy Zheng
3993ba71f7 anlogic: fix Makefile.inc 
During the addition of DRAM inferring support, the installation of
eagle_bb.v is accidentally removed.

Fix this issue.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
 2018-12-19 10:23:58 +08:00
Icenowy Zheng
c9513c695a Anlogic: let LUT5/6 have more cost than LUT4- 
According to the datasheet of Anlogic Eagle FPGAs, The LUTs natively
in an Anlogic FPGA is LUT4 (in MSLICEs) and "Enhanced LUT5" (in
LSLICEs). An "Enhanced LUT5" can be divided into two LUT4s.

So a LUT5 will cost around 2x resource of a LUT4, and a LUT6 will cost
2x resource of a LUT5.

Change the -lut parameter passed to the abc command to pass this cost
info to the ABC process.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
 2018-12-19 09:36:53 +08:00
Clifford Wolf
23bb77867f Minor style fixes 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-18 20:02:39 +01:00
Clifford Wolf
2d73e1b60a
Merge pull request #748 from makaimann/add-btor-ops 
Add btor ops for $mul, $div, $mod and $concat
 2018-12-18 19:59:29 +01:00
Clifford Wolf
eddf075d93
Merge pull request #751 from daveshah1/fix_589 
memory_dff: Fix typo when checking init value
 2018-12-18 19:55:42 +01:00
David Shah
2b16d4ed3d memory_dff: Fix typo when checking init value 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-12-18 17:40:01 +00:00
Clifford Wolf
fdf7c42181 Fix segfault in AST simplify 
(as proposed by Dan Gisselquist)

Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-18 17:49:38 +01:00
Clifford Wolf
3d671630e2 Improve src tagging (using names and attrs) of cells and wires in verific front-end 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-18 16:01:22 +01:00
Icenowy Zheng
7854d5ba21 anlogic: fix dbits of Anlogic Eagle DRAM16X4 
The dbits of DRAM16X4 is wrong set to 2, which leads to waste of DRAM
bits.

Fix the dbits number in the RAM configuration.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
 2018-12-18 14:38:44 +08:00
makaimann
abf5930a33 Add btor ops for $mul, $div, $mod and $concat 2018-12-17 10:45:17 -08:00
Clifford Wolf
847fd36077
Merge pull request #746 from Icenowy/anlogic-dram 
Support for DRAM inferring on Anlogic FPGAs
 2018-12-17 17:16:10 +01:00
Clifford Wolf
3b4290a1b8
Merge pull request #742 from whitequark/changelog 
Update CHANGELOG to mention my improvements
 2018-12-17 16:35:56 +01:00
Clifford Wolf
97b49d6e45
Merge pull request #741 from whitequark/ilang_slice_sigspec 
read_ilang: allow slicing all sigspecs, not just wires
 2018-12-17 16:29:25 +01:00
Clifford Wolf
ce701fd334
Merge pull request #744 from whitequark/write_verilog_$shift 
write_verilog: handle the $shift cell
 2018-12-17 16:26:57 +01:00
Icenowy Zheng
d53a2bd1d3 anlogic: add support for Eagle Distributed RAM 
The MSLICEs on the Eagle series of FPGA can be configured as Distributed
RAM.

Enable to synthesis to DRAM.

As the Anlogic software suite doesn't support any 'bx to exist in the
initializtion data of DRAM, do not enable the initialization support of
the inferred DRAM.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
 2018-12-17 23:20:40 +08:00
Icenowy Zheng
634d7d1c14 Revert "Leave only real black box cells" 
This reverts commit 43030db5ff.

For a synthesis tool, generating EG_LOGIC cells are a good choice, as
they can be furtherly optimized when PnR, although sometimes EG_LOGIC is
not as blackbox as EG_PHY cells (because the latter is more close to the
hardware implementation).

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
 2018-12-17 23:20:40 +08:00
Clifford Wolf
dc6e63d8cd
Merge pull request #745 from YosysHQ/revert-714-abc_preserve_naming 
Revert "Proof-of-concept: preserve naming through ABC using dress"
 2018-12-16 21:27:56 +01:00
Clifford Wolf
2641a3089b
Revert "Proof-of-concept: preserve naming through ABC using dress" 2018-12-16 21:27:31 +01:00
whitequark
ca866d384e write_verilog: handle the $shift cell. 
The implementation corresponds to the following Verilog, which is
lifted straight from simlib.v:

    module \\$shift (A, B, Y);

    parameter A_SIGNED = 0;
    parameter B_SIGNED = 0;
    parameter A_WIDTH = 0;
    parameter B_WIDTH = 0;
    parameter Y_WIDTH = 0;

    input [A_WIDTH-1:0] A;
    input [B_WIDTH-1:0] B;
    output [Y_WIDTH-1:0] Y;

    generate
        if (B_SIGNED) begin:BLOCK1
            assign Y = $signed(B) < 0 ? A << -B : A >> B;
        end else begin:BLOCK2
            assign Y = A >> B;
        end
    endgenerate

    endmodule
 2018-12-16 18:46:32 +00:00
whitequark
9f5c7017ff Update CHANGELOG. 2018-12-16 18:26:00 +00:00
whitequark
4effb38e6d read_ilang: allow slicing sigspecs. 2018-12-16 17:53:26 +00:00
Clifford Wolf
ddff75b60a
Merge pull request #736 from whitequark/select_assert_list 
select: print selection if a -assert-* flag causes an error
 2018-12-16 16:45:49 +01:00
whitequark
f6412d7109 select: print selection if a -assert-* flag causes an error. 2018-12-16 15:44:29 +00:00
Clifford Wolf
5fa5dbbdda Rename "fine:" label to "map:" in "synth_ice40" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-16 16:36:19 +01:00