mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-28 11:25:53 +00:00
Code Activity

Merge pull request #759 from whitequark/memory_collect_init_x

Browse source 
memory_collect: do not truncate 'x from \INIT
This commit is contained in:
Clifford Wolf 2018-12-21 17:39:52 +01:00 • committed by GitHub
commit 29a82acb2e
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
1 changed files with 0 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

3
passes/memory/memory_collect.cc
View file

@ -184,9 +184,6 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory)
mem->parameters["\\OFFSET"] = Const(memory->start_offset);
mem->parameters["\\SIZE"] = Const(memory->size);
mem->parameters["\\ABITS"] = Const(addr_bits);
while (GetSize(init_data) > 1 && init_data.bits.back() == State::Sx && init_data.bits[GetSize(init_data)-2] == State::Sx)
init_data.bits.pop_back();
mem->parameters["\\INIT"] = init_data;
log_assert(sig_wr_clk.size() == wr_ports);