226 commits

Author	SHA1	Message	Date
Clifford Wolf	c475deec6c	Switched to Python 3	2015-08-22 09:59:33 +02:00
Clifford Wolf	9596fe74de	Another bugfix for ice40 and xilinx brams_init make rules	2015-08-16 21:39:34 +02:00
Clifford Wolf	aedcfd6fd3	Fixed Makefile rules for generated share files	2015-08-16 21:15:07 +02:00
Clifford Wolf	d5b1a90b33	Added $tribuf and $_TBUF_ sim models	2015-08-16 13:05:32 +02:00
Clifford Wolf	9c33172ece	Added tribuf command	2015-08-16 12:55:25 +02:00
Clifford Wolf	ff50bc2ac3	Added $tribuf and $_TBUF_ cell types	2015-08-16 12:54:52 +02:00
Larry Doolittle	6c00704a5e	Another block of spelling fixes ... Smaller this time	2015-08-14 23:27:05 +02:00
Clifford Wolf	e4ef000b70	Adjust makefiles to work with out-of-tree builds ... This is based on work done by Larry Doolittle	2015-08-12 15:04:44 +02:00
Clifford Wolf	c43f38c81b	Improved handling of "keep" attributes in hierarchical designs in opt_clean	2015-08-12 14:10:14 +02:00
Marcus Comstedt	c9e56bc428	Added iCE40 WARMBOOT cell	2015-08-06 22:58:17 +02:00
Clifford Wolf	8d6d5c30d9	Added WORDS parameter to $meminit	2015-07-31 10:40:09 +02:00
Clifford Wolf	516e8828f2	Don't write a 17th memory bit in ice40/cells_sim (by Larry Doolittle)	2015-07-27 22:44:01 +02:00
Clifford Wolf	c6ca4780e2	iCE40 DFF sim models: init Q regs to 0	2015-07-20 13:05:18 +02:00
Clifford Wolf	54588a276a	Avoid tristate warning for blackbox ice40/cells_sim.v	2015-07-18 11:59:04 +02:00
Clifford Wolf	85aaf08e53	Improved liberty file test case	2015-07-06 17:45:56 +02:00
Clifford Wolf	f0c9a099d2	Added "synth -nofsm"	2015-07-02 15:25:38 +02:00
Clifford Wolf	6c84341f22	Fixed trailing whitespaces	2015-07-02 11:14:30 +02:00
Clifford Wolf	df0163cd2b	iCE40: set min bram efficiency to 2%	2015-06-20 09:31:19 +02:00
Clifford Wolf	ed128b82d7	Added "synth -nordff -noalumacc"	2015-06-15 17:07:40 +02:00
Clifford Wolf	9500b564ac	synth_ice40 now flattens by default	2015-06-09 20:28:17 +02:00
Clifford Wolf	09ef279b60	Added iCE40 PLL cells	2015-05-31 13:10:43 +02:00
Clifford Wolf	c329233f0d	Added output args to synth_ice40	2015-05-26 17:08:53 +02:00
Clifford Wolf	313f570fcc	improved ice40 SB_IO sim model	2015-05-23 10:17:03 +02:00
Clifford Wolf	264eb8eb6e	Added ice40 SB_IO sim model	2015-05-23 09:30:24 +02:00
Clifford Wolf	61512b6f41	Verific build fixes	2015-05-17 08:19:52 +02:00
Clifford Wolf	9d067fecea	ice40_opt bugfix	2015-04-27 11:36:13 +02:00
Clifford Wolf	310fde197e	iCE40: SB_CARRY const fold -> unmap SB_LUT	2015-04-27 10:27:50 +02:00
Clifford Wolf	794d22969d	Added simplemap $lut support	2015-04-27 10:16:07 +02:00
Clifford Wolf	8d4a675f91	Added iCE40 const folding support for SB_CARRY	2015-04-27 08:38:14 +02:00
Clifford Wolf	752851954b	Initialization support for all iCE40 bram modes	2015-04-26 08:39:31 +02:00
Clifford Wolf	b4d7a590e8	initialized iCE40 brams (mode 0)	2015-04-25 20:44:51 +02:00
Clifford Wolf	4cc4400514	improved iCE40 SB_RAM40_4K simulation model	2015-04-25 20:01:37 +02:00
Clifford Wolf	82a4722f46	More iCE40 bram improvements	2015-04-25 18:04:57 +02:00
Clifford Wolf	687f5a5b12	iCE40 bram progress	2015-04-24 15:38:11 +02:00
Clifford Wolf	308a59aa18	iCE40 bram tests and fixes	2015-04-24 08:32:07 +02:00
Clifford Wolf	d6f7698f59	Added ice40 bram support	2015-04-24 00:06:50 +02:00
Clifford Wolf	1277d1bcb8	iCE40: Added SB_RAM40_4K{,NR,NW,NRNW}* models	2015-04-19 21:37:40 +02:00
Clifford Wolf	49ef830464	added sync reset to ice40 test_ffs.sh	2015-04-18 09:41:31 +02:00
Clifford Wolf	f564a65851	Added ice40 test_arith	2015-04-18 09:33:34 +02:00
Clifford Wolf	f78fa718be	Added ice40 SB_CARRY support	2015-04-18 09:33:08 +02:00
Clifford Wolf	661b647559	Added mapping of synchronous set/reset to iCE40 flow	2015-04-17 11:54:25 +02:00
Clifford Wolf	31755ed1cf	Changed ice40 ICESTORM_CARRYCONST port name	2015-04-16 12:09:14 +02:00
Clifford Wolf	dc30b034f7	Fixed "dff2dffe -direct-match"	2015-04-16 11:47:59 +02:00
Clifford Wolf	3e9e6e1c22	Added simple ice40 dff tests	2015-04-16 11:31:15 +02:00
Clifford Wolf	0d344a23d3	improved ice40 dff cell mapping	2015-04-16 11:30:56 +02:00
Clifford Wolf	4529c56cc6	use "hierarchy -auto-top" in synth_ice40	2015-04-14 13:45:15 +02:00
Clifford Wolf	06ce496f8d	more cells in ice40 cell library	2015-04-14 13:44:43 +02:00
Clifford Wolf	3481f46d1e	Improved xilinx "bram1" test	2015-04-09 17:12:12 +02:00
Clifford Wolf	7319951145	Added memory_bram "make_outreg" feature	2015-04-09 16:08:54 +02:00
Clifford Wolf	229825e1b8	Xilinx DRAMS: RAM64X1D, RAM128X1D	2015-04-09 13:37:07 +02:00