2436 commits

Author	SHA1	Message	Date
Andrew Zonenberg	634f18be96	extract_counter: Minor changes requested to comply with upstream policy, fixed a few typos	2017-08-30 16:28:25 -07:00
Andrew Zonenberg	3fc1b9f3fd	Finished refactoring counter extraction to be nice and generic. Implemented techmapping from $__COUNT_ to GP_COUNTx cells.	2017-08-28 22:18:57 -07:00
Andrew Zonenberg	b5c15636c5	Refactoring: Renamed greenpak4_counters pass to extract_counter, moved it to techmap/ since it's going to become a generic pass	2017-08-28 22:18:34 -07:00
Andrew Zonenberg	c3145863e7	Reformatted GP_COUNTx_ADV resets to avoid Yosys thinking that they're multi-edge-sensitive and getting confused.	2017-08-28 14:25:46 -07:00
Andrew Zonenberg	e62362225c	Fixed bug causing GP_SPI model to not synthesize	2017-08-27 07:31:48 -07:00
Andrew Zonenberg	e6eaf487b6	Fixed more issues with GreenPAK counter sim models	2017-08-15 09:18:36 -07:00
Andrew Zonenberg	3a404be62a	Updated PGEN model to have level triggered reset (matches actual hardware behavior	2017-08-15 09:18:27 -07:00
Andrew Zonenberg	e5109847c9	Fixed bug in GP_COUNTx model	2017-08-15 09:18:17 -07:00
Andrew Zonenberg	66b256d40e	Fixed bug where GP_COUNTx_ADV would wrap even when KEEP was high	2017-08-15 09:18:07 -07:00
Clifford Wolf	2cf0b5c157	Merge pull request #381 from azonenberg/countfix ... Added better behavioral models for GreenPAK counters. Refactored cells_sim into two files so analog/mixed signal stuff is separate	2017-08-14 21:47:26 +02:00
Robert Ou	78fd24f40f	coolrunner2: Add INVERT parameter to some BUFGs	2017-08-14 12:13:33 -07:00
Robert Ou	1e3ffd57cb	coolrunner2: Add FFs with clock enable to cells_sim.v	2017-08-14 12:13:25 -07:00
Andrew Zonenberg	348acbd968	Fixed typo in GP_COUNT8 sim model	2017-08-14 10:45:40 -07:00
Andrew Zonenberg	c205d571df	Fixed typo in error message	2017-08-14 10:45:40 -07:00
Andrew Zonenberg	0a6c702c41	Changed LEVEL resets for GP_COUNTx to be properly synthesizeable	2017-08-14 10:45:40 -07:00
Andrew Zonenberg	9f3dc59ffe	Changed LEVEL resets to be edge triggered anyway	2017-08-14 10:45:40 -07:00
Andrew Zonenberg	b049ead042	Added level-triggered reset support to GP_COUNTx simulation models	2017-08-14 10:45:40 -07:00
Andrew Zonenberg	ac75524f69	Fixed undeclared "count" in GP_COUNT8_ADV	2017-08-14 10:45:39 -07:00
Andrew Zonenberg	db20e3f1c2	Fixed undeclared "count" in GP_COUNT14_ADV	2017-08-14 10:45:39 -07:00
Andrew Zonenberg	3618ca2218	Fixed typo in last commit	2017-08-14 10:45:39 -07:00
Andrew Zonenberg	4da1a327c0	Finished initial GP_COUNT8/14/8_ADV/14_ADV sim models. Don't support clock divide, but do everything else.	2017-08-14 10:45:39 -07:00
Andrew Zonenberg	4504dd78e9	Fixed typo in COUNT8 model	2017-08-14 10:45:39 -07:00
Andrew Zonenberg	60dd5dba7b	Moved GP_POR out of digital cells b/c it has delays	2017-08-14 10:45:39 -07:00
Andrew Zonenberg	f55d4cc2fd	Improved cells_sim_digital model for GP_COUNT8	2017-08-14 10:45:39 -07:00
Andrew Zonenberg	fe3a932cfa	Refactored GreenPAK4 cells_sim into cells_sim_ams and cells_sim_digital	2017-08-14 10:45:39 -07:00
Clifford Wolf	8a69759306	Add techlibs/xilinx/lut2lut.v	2017-07-10 12:09:05 +02:00
Clifford Wolf	621787a9e0	Fix some c++ clang compiler errors	2017-07-03 19:38:30 +02:00
Clifford Wolf	5c1c126374	Apply minor coding style changes to coolrunner2 target	2017-07-03 19:35:40 +02:00
Clifford Wolf	6afee022ad	Merge pull request #352 from rqou/master ... Initial Coolrunner-II support	2017-07-03 19:33:36 +02:00
Robert Ou	b102c0e254	coolrunner2: Add a few more primitives ... These cannot be inferred yet, but add them to cells_sim.v for now	2017-06-25 23:58:28 -07:00
Robert Ou	36b75dfcb7	coolrunner2: Initial mapping of latches	2017-06-25 23:58:28 -07:00
Robert Ou	4af5baab21	coolrunner2: Initial mapping of DFFs ... All DFFs map to either FDCP (matches Xilinx) or a custom FDCP_N (negative-edge triggered)	2017-06-25 23:58:28 -07:00
Robert Ou	1eb5dee799	coolrunner2: Remove redundant INVERT_PTC	2017-06-25 23:58:28 -07:00
Robert Ou	ffff001008	coolrunner2: Remove debug prints	2017-06-25 23:58:28 -07:00
Robert Ou	5798105d47	coolrunner2: Correctly handle $_NOT_ after $sop	2017-06-25 23:58:28 -07:00
Robert Ou	908ce3fdce	coolrunner2: Also construct the XOR cell in the macrocell	2017-06-25 23:58:28 -07:00
Robert Ou	a64b56648d	coolrunner2: Initial techmapping for $sop	2017-06-25 23:58:22 -07:00
Andrew Zonenberg	cbdddc3af9	greenpak4_counters: Changed generation of primitive names so that the absorbed register's name is included	2017-06-24 14:54:07 -07:00
Robert Ou	6e0fb889fa	coolrunner2: Initial commit	2017-06-24 07:22:56 -07:00
Clifford Wolf	e7a984a4df	Add dff2ff.v techmap file	2017-05-31 11:45:58 +02:00
Andrew Zonenberg	184bd148c9	greenpak4_counters: Added support for parallel output from GP_COUNTx cells	2017-05-22 19:39:55 -07:00
Clifford Wolf	05cdd58c8d	Add $_ANDNOT_ and $_ORNOT_ gates	2017-05-17 09:08:29 +02:00
Larry Doolittle	2021ddecb3	Squelch trailing whitespace	2017-04-12 15:11:09 +02:00
dh73	c27dcc1e47	Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAs	2017-04-05 23:01:29 -05:00
Clifford Wolf	f3324ed0cc	Merge branch 'master' of github.com:cliffordwolf/yosys	2017-02-25 13:08:27 +01:00
Clifford Wolf	5f1d0b1024	Add $live and $fair cell types, add support for s_eventually keyword	2017-02-25 10:36:39 +01:00
Andrew Zonenberg	6fed2dc996	Merge https://github.com/cliffordwolf/yosys	2017-02-14 08:29:37 -08:00
Clifford Wolf	2a311c2c38	Fix double-call of log_pop() in synth_greenpak4	2017-02-14 11:57:54 +01:00
Andrew Zonenberg	0d7e71f7ab	Merge https://github.com/cliffordwolf/yosys	2017-02-08 22:12:29 -08:00
Clifford Wolf	3928482a3c	Add $cover cell type and SVA cover() support	2017-02-04 14:14:26 +01:00