The YosysHQ Verific Extensions are compiled separately using their own
stripped-down version of the Yosys headers. To maintain ABI
compatibility with older extension builds post C++-ification of Yosys's
logging APIs, which are backwards compatible on the API but not ABI
level, this commit adds ABI compatible versions of a subset of the old
logging API used by the extensions.
The code in memory_libmap expects `clk_en` to be initialized for all
`PortVariant`s but the parsing in memlib.cc didn't initialize it for
variants of kind `PortKind::Ar` (async read ports).
While this fixes the immediate CI failure, it would be best to refactor
the code so it becomes obvious if something isn't initialized.
The ID(OVERFLOW) IdString isn't used widely enough that we require a
statically allocated IdString, but I think it's good to have an example
workaround in place in case more collisions come up.
I've used this shell command to obtain the list:
rg -I -t cpp -t yacc -o \
'ID\((\$?[a-zA-Z0-9_]+)\)|ID::($?[a-zA-Z0-9_]+)' -r 'X($1$2)' \
| LC_ALL=C sort -u
This removed the entries X(_TECHMAP_FAIL_) and X(nomem2init).
The vast majority of ID(...) uses are in a context that is overloaded
for StaticIdString or will cause implicit conversion to an IdString
constant reference. For some sufficently overloaded contexts, implicit
conversion may fail, so it's useful to have a method to force obtaining
a `IdString const &` from an ID(...) use.
When turning all literal IdStrings of the codebase into StaticIdStrings
this was needed in exactly one place, for which this commit adds an
`id_string()` call.
* When used with -tempinduct mode, -seq <N> causes assertions to be
ignored in the first N steps. While this has uses for reset modelling,
for these test cases it is unnecessary and could lead to failures
slipping through uncaught
Commit c8e0ac0 introduces a regression on handling case exprs that look
like sva labels. After some debugging, we shouldn't push the identifier
ast node to the ast_stack, otherwise, we will get the following
assertion failure:
```
➜ /tmp yosys -p 'read -sv a1.v'
/----------------------------------------------------------------------------\
| yosys -- Yosys Open SYnthesis Suite |
| Copyright (C) 2012 - 2025 Claire Xenia Wolf <claire@yosyshq.com> |
| Distributed under an ISC-like license, type "license" to see terms |
\----------------------------------------------------------------------------/
Yosys 0.57+1 (git sha1 baa61a146, clang++ 20.1.8 -fPIC -O3)
-- Running command `read -sv a1.v' --
1. Executing Verilog-2005 frontend: a1.v
Parsing SystemVerilog input from `a1.v' to AST representation.
ERROR: Assert `extra->ast_stack.size() == 1' failed in frontends/verilog/verilog_parser.y:709.
➜ /tmp cat a1.v
module test(input wire A);
localparam TEST = 1;
always_comb begin
case (A)
TEST: assert(1);
endcase
end
endmodule
```
We encountered this issue before but with a different error message[^1],
[^1]: https://github.com/YosysHQ/yosys/issues/862
When FILTERLIB is defined (attempts to compile libparse more or less standalone,) mark the `LibertyParser::error()` as weak so utilities using libparse as a library can override its behavior (the default behavior being exit(1)). As the code is quite performance-critical, I've elected to not modify it to raise an exception or have a callback or similar and simply allow for a link-time replacement.
