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Merge pull request #5330 from higuoxing/fix-sva-in-case-expr

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Fix handling of cases that look like sva labels again.
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Emil J 2025-09-05 20:10:56 +02:00 • committed by GitHub
commit db7aa538f9
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2 changed files with 12 additions and 1 deletions
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3
frontends/verilog/verilog_parser.y
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@ -3023,7 +3023,8 @@ case_expr_list:
SET_AST_NODE_LOC(node, @1, @1);
} |
TOK_SVA_LABEL {
AstNode* node = extra->pushChild(std::make_unique<AstNode>(@$, AST_IDENTIFIER));
AstNode* node = extra->saveChild(std::make_unique<AstNode>(@$, AST_IDENTIFIER));
node->str = *$1;
SET_AST_NODE_LOC(node, @1, @1);
} |
expr {

10
tests/verilog/sva-in-case-expr.ys Normal file
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@ -0,0 +1,10 @@
read_verilog -sv <<EOT
module test(input wire A);
localparam TEST = 1;
always_comb begin
case (A)
TEST: assert(1);
endcase
end
endmodule
EOT