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Code Activity
6333 commits 99 branches 53 tags 47 MiB
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1952 commits

Author SHA1 Message Date
Eddie Hung
3f34779d64 Do not call "setundef -zero" in abc9 2019-06-20 17:38:04 -07:00
Eddie Hung
e63324f5ef Actually, there might not be any harm in updating sigmap... 2019-06-20 17:03:05 -07:00
Eddie Hung
9c61fb0e0c Add comment as per @cliffordwolf 2019-06-20 16:57:54 -07:00
Ben Widawsky
8767ec3fbd Add a few more filename rewrites 
This now allows a full pipeline to work, something such as:
yosys -p "synth_ecp5 -json ~/work/fpga/prjtrellis/examples/ecp5_evn/blinky.v"

Otherwise, you will get something along the lines of:
ERROR: Can't open output file `~/work/fpga/prjtrellis/examples/ecp5_evn/blinky.v' for writing: No such file or directory

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2019-06-20 10:27:59 -07:00
Clifford Wolf
477e566e8d Fix typo, fixes #1095 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-20 15:34:52 +02:00
Clifford Wolf
06eb87bcb7 Improve shregmap help message, fixes #1113 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-20 15:23:55 +02:00
Clifford Wolf
2454ad99bf Refactor "opt_rmdff -sat" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-20 13:44:21 +02:00
Clifford Wolf
73bd1d59a7 Merge branch 'master' of https://github.com/bogdanvuk/yosys into clifford/ext1046 2019-06-20 13:04:04 +02:00
Clifford Wolf
11ec7b2aec Fix typo 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-20 12:23:07 +02:00
acw1251
0d888ee7ed Fixed the help summary line for a few commands 2019-06-19 15:27:04 -04:00
Eddie Hung
96ade54993 Fix bug in #1078, add entry to CHANGELOG 2019-06-19 09:51:11 -07:00
Clifford Wolf
3da5288ce0 Use input default values in hierarchy pass 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-19 11:49:20 +02:00
Eddie Hung
4d6d593fe3 &scorr before &sweep, remove &retime as recommended 2019-06-17 13:32:08 -07:00
Eddie Hung
63fc879a5f Copy not move parameters/attributes 2019-06-17 13:19:45 -07:00
Eddie Hung
b45d06d7a3 Fix leak removing cells during ABC integration; also preserve attr 2019-06-17 12:54:24 -07:00
Eddie Hung
7250c57c5a Re-enable &dc2 2019-06-17 10:28:51 -07:00
Eddie Hung
fb90d8c18c Cleanup 2019-06-16 09:34:26 -07:00
Eddie Hung
2d85725604 Get rid of compiler warnings 2019-06-14 13:07:56 -07:00
Eddie Hung
a632799d5b Update abc9 -D doc 2019-06-14 12:29:46 -07:00
Eddie Hung
e391fc8e7b Enable "abc9 -D <num>" for timing-driven synthesis 2019-06-14 12:28:01 -07:00
Eddie Hung
a48b5bfaa5 Further cleanup based on @daveshah1 2019-06-14 12:25:06 -07:00
Eddie Hung
751e640c1d Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig 2019-06-14 10:29:16 -07:00
Eddie Hung
a5425a2f7e Remove extra semicolon 2019-06-14 10:11:34 -07:00
David Shah
9566573054 ecp5: Add abc9 option 
Signed-off-by: David Shah <dave@ds0.me>
 2019-06-14 17:15:02 +01:00
Bogdan Vukobratovic
8451cbea89 Move netlist helper module to passes/opt for the time being 2019-06-14 12:14:02 +02:00
Bogdan Vukobratovic
fe651922cb Merge remote-tracking branch 'upstream/master' 2019-06-14 12:06:57 +02:00
Bogdan Vukobratovic
53695e6729 Prepare for situation when port of the signal cannot be found 2019-06-14 11:39:24 +02:00
Bogdan Vukobratovic
291b36afeb Some cleanup, revert sat.cc 2019-06-14 11:35:45 +02:00
Bogdan Vukobratovic
8665f48879 Implement disconnection of constant register bits 2019-06-13 19:35:37 +02:00
Eddie Hung
2c40b66785 Rip out all non FPGA stuff from abc9 2019-06-12 16:53:12 -07:00
Eddie Hung
f81a189fb8 Fix spelling 2019-06-12 16:52:09 -07:00
Eddie Hung
90dc4d82de Revert "For 'stat' do not count modules with abc_box_id" 
This reverts commit b89bb74452.
 2019-06-12 16:51:37 -07:00
Eddie Hung
b3faf0246d Be more precise when connecting during ABC9 re-integration 2019-06-12 16:04:33 -07:00
Eddie Hung
2e7e73f483 Remove hacky wideports_split from abc9 2019-06-12 15:52:49 -07:00
Eddie Hung
d9974b85e7 Fix compile errors when #if 1 for debug 2019-06-12 15:47:39 -07:00
Bogdan Vukobratovic
d69989b8d2 Rename satgen_algo.h -> algo.h, code cleanup and refactoring 2019-06-12 19:35:05 +02:00
Eddie Hung
8bb67fa67c Do not call abc9 if no outputs 2019-06-12 10:18:44 -07:00
Eddie Hung
14e870d4c4 More write_xaiger cleanup 2019-06-12 10:00:57 -07:00
Eddie Hung
b21d29598a Consistency 2019-06-12 09:40:51 -07:00
Eddie Hung
b2c72f74f0 Merge branch 'xc7mux' into xaig 2019-06-12 09:14:27 -07:00
Eddie Hung
afd620fd5f Typo: wire delay is -W argument 2019-06-12 09:13:53 -07:00
Eddie Hung
2cbcd6224c Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux" 
This reverts commit a138381ac3, reversing
changes made to b77c5da769.
 2019-06-12 09:05:02 -07:00
Eddie Hung
882a83c383 Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux" 
This reverts commit eaee250a6e, reversing
changes made to 935df3569b.
 2019-06-12 09:04:31 -07:00
Eddie Hung
86efe9a616 Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux" 
This reverts commit 2223ca91b0, reversing
changes made to eaee250a6e.
 2019-06-12 09:01:15 -07:00
Eddie Hung
1e838a8913 Retry "Add "-W' wire delay arg to abc9, use from synth_xilinx" 2019-06-12 08:49:15 -07:00
Eddie Hung
4c9fde87d1 Revert "Add "-W' wire delay arg to abc9, use from synth_xilinx" 
This reverts commit 2dffa4685b.
 2019-06-12 08:48:45 -07:00
Eddie Hung
2dffa4685b Add "-W' wire delay arg to abc9, use from synth_xilinx 2019-06-11 17:10:47 -07:00
Eddie Hung
6cdea93724 Revert "Try way that doesn't involve creating a new wire" 
This reverts commit 2f427acc9e.
 2019-06-11 16:05:42 -07:00
Eddie Hung
d26646051c Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux" 
This reverts commit 5174082208, reversing
changes made to 54379f9872.
 2019-06-11 16:05:27 -07:00
Eddie Hung
5174082208 Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux 2019-06-11 15:48:41 -07:00